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| this product p revie w d ata s heet contains preliminary information w h ich may be s ubject to change ethermap-12 microprocessor telecom bus side ethernet line side txc-04212 interface ethernet into sts-12/stm-4 sonet/sdh mapper drop bus add bus sdram interface +3.3v +1.2v ho/lo ring ports ho/lo poh ports clocks (sonet/sdh ref, system, one sec.) ethernet management interface controls 10/100 mbit/s smii (port 1) 10/100 mbit/s smii (port 8) / 1000 mbit/s gmii ? stm-4/sts-12 77 mhz ? eight 10/100 mbit/s ethernet ports, each using a smii inter- face single 1000 mbit/s ethernet port, using a parallel gmii inter- face (lead shared with smii interfaces) ethernet management interface for control and configura- tion of externally connected phys gmii mux-mode allowing multiple concatenation groups from one gmii supports ieee 802.3 flow control (half and full-duplex) and management statistics (rmon) on 10/100/1000 mbit/s ethernet ports (100 mbps full-duplex only) ethernet frame encapsulation/decapsulation protocols: itu-t g.7041, generic framing procedure (gfp) itu-t x.86/x.85, link access procedure sdh (laps) itu-t q.922, link access procedure frame mode (lapf) ietf rfc2878, point-to-point protocol (ppp) with bridging control protocol (bcp) support transparent hdlc processing performs mapping/demapping of encapsulated ether- net frames into/from low order virtual concatenated payloads and high order virtual and contiguous concate- nated payloads dynamic bandwidth allocation using lcas (itu-t g.7042) for low and high order virtual concatenated payloads glueless memory interface to external sdrams (up to 256 mb) low order poh and pointer processing for 336/252 vt/tus high order poh and pointer processing for sts-1/vc-3/ sts-3c/vc-4, sts-6c, sts-9c and sts-12c/vc4-4c byte-wide 77.76mhz add /drop line telecom bus inter- faces per-port ethernet side and sonet/sdh system side loop- back for system level diagnostics 16-bit wide microprocessor interface, selectable between motorola or intel api based driver provided (comparable with ethermap-3) boundary scan (ieee 1149.1 standard) + 3.3v and +1.2v power supplies, 5v tolerant i/o leads 580-lead plastic ball grid array package (pbga) document number: product preview txc-04212-mb, ed. 2 november 2003 data sheet product preview ethermap ? -12 device ethernet into sts-12/stm-4 sonet/sdh mapper txc-04212 the ethermap ? -12 is a highly integrated, sts-12/stm-4 rate sonet/sdh device that provides mapping of 10/100/1000 mbps ethernet traffic into sonet/sdh transport structures. the ethermap-12 has on the ethernet side, either eight 10/100 mbps smii mac interfaces or one independent 1000 mbps gmii mac interface. over-subscription is allowed for example in map- ping one gigabit ethernet stream into either a single vc-4- 4c/sts12c spe, multiple vc-4/sts-3c spes, or multiple vc- 3s/sts-1 spes is supported via configuration and built-in flow con- trol mechanisms. the sts-12/stm-4 front-end of the device is a standard byte wide 77.76 mhz telecom bus interface sonet processing includes low and high order pointer tracking and retiming, low and high order poh processing and performance monitoring along with complete high order and low order virtual concatenation with lcas. both vt/tu and sts-1/vc-3 level non-blocking cross connects are available for flexible data path grooming and switching. the device operates from a 1.2v core and 3.3v/io power supplies. a fully functional device driver is available through transwitch applications engineering. sonet/sdh add/drop and terminal multiplexers multi-service access platforms ip dslams cpe access platforms wireless backhaul multiplexors proprietary transwitch corporation information for use solely by its customers product preview information documents contain information on products in their formative or design phase of development. features, characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product. u.s. and/or foreign patents issued or pending copyright ? 2003 transwitch corporation ethermap is a trademark of transwitch corporation phast, temx28, transwitch and txc are registered trademarks of transwitch corporation applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 table of contents section page list of figures ............................................................................................................... .................... 5 list of tables ................................................................................................................ .................... 6 features ...................................................................................................................... ..................... 7 general device level .......................................................................................................... ...... 7 sonet/sdh mappings: ........................................................................................................... . 7 sonet/sdh tx mapper .................................................................................................... 8 sonet/sdh rx demapper ............................................................................................... 9 virtual concatenation ......................................................................................................... ..... 10 tx and rx eos processors ..................................................................................................... 10 ethernet ports ................................................................................................................ ......... 10 10/100/1000 mbps ethernet mac blocks ............................................................................... 11 sdram interfaces .............................................................................................................. .... 11 microprocessor interface ...................................................................................................... ... 11 jtag interface ................................................................................................................ ........ 11 device driver ................................................................................................................. .......... 11 block diagram ................................................................................................................. ............... 12 block diagram description ..................................................................................................... ........ 13 ethermap-12 device interfaces ............................................................................................... 1 4 10/100 mbps ethernet smii .................................................................................................... 14 1000 mbps ethernet gmii ....................................................................................................... 14 ethernet management interface .............................................................................................. 14 microprocessor interface ...................................................................................................... ... 14 sdram memory interfaces ..................................................................................................... 1 4 parallel line side telecom bus interface ............................................................................... 15 high & low order poh port interface .................................................................................... 15 high & low order alarm indication port interface .................................................................. 15 jtag interface ................................................................................................................ ........ 15 ethernet over sonet sdh mapping ..................................................................................... 16 data processing/flow .......................................................................................................... .... 17 application examples .......................................................................................................... ........... 20 lead diagram .................................................................................................................. ............... 21 lead descriptions ............................................................................................................. .............. 22 absolute maximum ratings and environmental limitations (referenced to vss) ........................ 45 thermal characteristics ....................................................................................................... ........... 45 power requirements ............................................................................................................ .......... 45 input, output and input/output parameters ................................................................................... 4 6 timing characteristics ........................................................................................................ ............ 50 operation ..................................................................................................................... ................... 87 sonet/sdh processing ........................................................................................................ 8 7 mapper block .................................................................................................................. ............... 89 high order path ............................................................................................................... ....... 89 low order path ................................................................................................................ ....... 90 demapper block ................................................................................................................ ............. 91 high order path ............................................................................................................... ....... 91 low order path ................................................................................................................ ....... 92 transmit high order path termination (vc-3/vc-4/vc-4-xc/sts-1/sts-nc poh generator) ................................................................................................................ ...... 93 receive high order path termination (vc-3/vc-4/vc-4-xc/sts-1/sts-nc poh monitor) .................................................................................................................. ........ 94 high order poh port interface ............................................................................................... 9 6 high order alarm indication port interface ............................................................................. 96 sts-1/au-3/au-4 pointer generation ..................................................................................... 98 tu-3 pointer generation ....................................................................................................... .. 98 tu-3 pointer tracking ......................................................................................................... .... 98 vc-3/sts-1/tug-3 cross connect ........................................................................................ 98 tu/vt pointer tracking ........................................................................................................ ... 98 tu/vt pointer generation ...................................................................................................... . 98 - 3 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 table of contents (cont.) section page low order cross connect ...................................................................................................... 99 transmit low order path termination (low order poh generator) ...................................... 99 receive low order path termination (low order poh monitor) ......................................... 100 low order poh port interface .............................................................................................. 102 low order alarm indication port interface ............................................................................ 103 virtual concatenation and lcas ................................................................................................ . 104 low order virtual concatenation without lcas ................................................................... 105 low order virtual concatenation with lcas ........................................................................ 108 high order virtual concatenation without lcas .................................................................. 109 high order virtual concatenation with lcas ....................................................................... 112 configuration ................................................................................................................. ........ 113 general ....................................................................................................................... ... 113 differential delay compensation .......................................................................................... 115 maximum differential delay allowed ............................................................................. 115 maximum differential delay detected ........................................................................... 116 ethernet line interfaces ...................................................................................................... ......... 117 ethernet mac blocks ........................................................................................................... ........ 119 ethernet half duplex .......................................................................................................... .......... 120 carrier sense ................................................................................................................. ....... 120 collision detection ........................................................................................................... ..... 120 alternate beb truncation ..................................................................................................... 120 excessive collisions .......................................................................................................... ... 120 half-duplex flow control ...................................................................................................... 121 flow control operation ........................................................................................................ ........ 122 encapsulation / decapsulation ................................................................................................. .... 124 gfp ........................................................................................................................... ............ 125 gfp host extraction of management/control frames .......................................................... 133 gfp linear frame mode operation ..................................................................................... 134 transmit side linear extension header ........................................................................ 134 transmit side cid configuration tables ....................................................................... 134 receive side linear extension header ......................................................................... 136 receive side cid configuration tables ........................................................................ 136 laps .......................................................................................................................... ........... 138 lapf .......................................................................................................................... ........... 147 ppp (with bcp and lcp support) ........................................................................................ 155 transparent hdlc .............................................................................................................. .. 168 gmii mux-mode ................................................................................................................. .......... 171 sdram controllers ............................................................................................................. ......... 172 sdram memory interfaces .................................................................................................. 172 cas latency .................................................................................................................. 172 bank/row activation ................................................................................................... 172 commands .................................................................................................................... 1 73 reset configuration of sdram controller ............................................................................ 173 configuration changes/initialization ..................................................................................... 173 microprocessor access to sdram ....................................................................................... 174 reset operation ............................................................................................................... ............ 175 general ....................................................................................................................... .......... 175 external lead controlled hardware reset ........................................................................... 175 microprocessor controlled hardware reset ......................................................................... 175 microprocessor controlled soft reset .................................................................................. 175 microprocessor controlled global performance counter reset ........................................... 175 telecom bus operation ......................................................................................................... ...... 176 general ....................................................................................................................... .......... 176 drop bus interface ............................................................................................................ .... 176 drop bus parity selection ..................................................................................................... 177 add bus interface ............................................................................................................. .... 177 add bus timing modes ......................................................................................................... 178 - 4 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 table of contents (cont.) section page add bus parity selection ...................................................................................................... . 179 add indicator invert .......................................................................................................... ..... 179 add bus delay ................................................................................................................. ..... 179 force vc-3 or vc-4 time slots to high impedance ............................................................... 180 force tug-3 time slots to high impedance .......................................................................... 180 force tug-2 time slots to high impedance .......................................................................... 180 force tu-11/tu-12 time slots to high impedance ................................................................ 180 boundary scan ................................................................................................................. ..... 181 introduction .................................................................................................................. .. 181 boundary scan operation .............................................................................................. 181 boundary scan reset .................................................................................................... 181 alarms, performance and fault monitoring .................................................................................. 183 terminology ................................................................................................................... ....... 183 system alarm (raw, unlatched alarm) .......................................................................... 183 alarm event ................................................................................................................... 183 latched alarm ................................................................................................................ 183 secondary alarm inhibition ............................................................................................ 183 trail signal failure (tsf) ............................................................................................... 183 server signal failure (ssf) ........................................................................................... 183 interrupt mask ................................................................................................................ 184 performance and fault monitoring (pm and fm) ........................................................... 184 performance monitoring (pm) ........................................................................................ 184 fault monitoring (fm) ..................................................................................................... 184 1-second clock .............................................................................................................. 1 84 performance counters ................................................................................................... 184 unlatched alarms .............................................................................................................. .... 185 inhibition of secondary unlatched alarm generation .................................................... 185 latched alarms ................................................................................................................ ..... 185 latched alarm bits for interrupt generation (lalarm_name/l1alarm_name) ....................... 186 latched alarm masking bits (malarm_name) ....................................................................... 187 secondary latched alarm inhibition ..................................................................................... 188 latched alarm bits for pm/fm (l2alarm_name), performance monitoring (pm bits; palarm_name) and fault monitoring (fm bits; falarm_name) .............................. 189 positive edge events ..................................................................................................... 190 negative edge events ................................................................................................... 191 positive or negative edge events .................................................................................. 192 overall alarm generation and pm/fm process diagram ...................................................... 193 performance counters .......................................................................................................... 194 scheme a - counters with roll-over/saturation option ................................................ 194 scheme b - performance counters with 1-second shadow register option ................ 194 alarm feature combinations ................................................................................................ 195 system alarm, interrupt, and pm/fm hierarchy .................................................................... 196 mapper/demapper performance monitoring ......................................................................... 198 package information ........................................................................................................... ......... 199 ordering information .......................................................................................................... .......... 200 related products .............................................................................................................. ............ 200 reference documents ........................................................................................................... ....... 201 standards documentation sources .............................................................................................. 202 list of data sheet changes .................................................................................................... ..... 204 please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com . customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. - 5 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 list of figures figure page 1. functional block diagram of the ethermap-12 .................................................................... 12 2. mapping of ethernet frames over sonet/sdh ................................................................ 16 3. low order virtual concatenation structure for sonet ...................................................... 17 4. high order virtual concatenation structure for sonet/sdh ............................................. 18 5. vc-4-xc/sts-nc (n = 3x) contiguous concatenation structure for sonet/sdh ............. 19 6. ethermap-12 txc-04212 lead diagram ............................................................................. 21 7. drop bus timing ............................................................................................................. ..... 50 8. add bus timing (timing signals are inputs) ....................................................................... 51 9. add bus timing (timing signals are outputs) ..................................................................... 52 10. tx gmii ethernet interface ................................................................................................. . 53 11. rx gmii ethernet interface ................................................................................................. 54 12. tx/rx smii ethernet interface (with sync as output) ........................................................ 55 13. tx/rx smii ethernet interface (with sync as input) .......................................................... 56 14. ethernet management interface .......................................................................................... 57 15. sdram interface - single word read ................................................................................ 58 16. sdram interface - single word write ................................................................................ 59 17. sdram interface - burst read ........................................................................................... 60 18. sdram interface - burst write ........................................................................................... 61 19. rx high order poh byte interface ..................................................................................... 62 20. tx high order poh byte interface ..................................................................................... 63 21. rx low order poh byte interface ...................................................................................... 64 22. tx low order poh byte interface ...................................................................................... 65 23. rx high order alarm indication port interface .................................................................... 66 24. tx high order alarm indication port interface .................................................................... 67 25. rx low order alarm indication port interface .................................................................... 68 26. tx low order alarm indication port interface ..................................................................... 69 27. microprocessor interface: generic intel mode write cycle ................................................. 70 28. microprocessor interface: generic intel mode read cycle ................................................. 72 29. microprocessor interface: generic motorola mode write cycle .......................................... 74 30. microprocessor interface: generic motorola mode read cycle .......................................... 76 31. microprocessor interface: motorola mpc860 mode write cycle ......................................... 78 32. microprocessor interface: motorola mpc860 mode read cycle ........................................ 80 33. microprocessor interface: motorola mpc8260 local bus mode write cycle ...................... 82 34. microprocessor interface: motorola mpc8260 local bus mode read cycle ...................... 84 35. boundary scan timing ....................................................................................................... . 86 36. functional block diagram of the mapper/demapper ........................................................... 87 37. functional model of the mapper/demapper ........................................................................ 88 38. vt1.5-xv-spe structure ................................................................................................... 1 05 39. vc-11-xv structure ......................................................................................................... .. 106 40. lo sdh multiplexing structure 1 supported by the ethermap-12 .................................... 106 41. lo sdh multiplexing structure 3 supported by the ethermap-12 .................................... 107 42. lo sdh multiplexing structure 2 supported by the ethermap-12 .................................... 107 43. lo sonet multiplexing structure supported by the ethermap-12 ................................... 107 44. sts-1-xv-spe structure ................................................................................................... 1 09 45. vc-3-xv structure .......................................................................................................... ... 110 46. ho sdh multiplexing structure supported by the ethermap-12 ....................................... 111 47. ho sonet multiplexing structure supported by the ethermap-12 .................................. 111 48. ethermap-12 to phy or switch interconnection using gmii interface .............................. 118 49. format of gfp frame with an ethernet mac frame payload .......................................... 125 50. format of laps frame with an ethernet mac frame payload ........................................ 138 51. format of lapf bridged frame with an ethernet mac frame payload ........................... 147 52. format of ppp frame with an ethernet mac frame payload .......................................... 155 53. format of transparent hdlc frame with an ethernet mac frame payload ................... 168 54. gmii mux-mode application overview .............................................................................. 171 - 6 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 list of figures (cont.) figure page 55. boundary scan schematic ................................................................................................ 182 56. latched alarm bit (l1alarm_name) transitions ................................................................ 187 57. positive edge event - pm/fm signal generation .............................................................. 190 58. negative edge event - pm/fm signal generation ............................................................ 191 59. positive/negative edge event - pm/fm signal generation ............................................... 192 60. alarm, interrupt and pm/fm generation process .............................................................. 193 61. alarm, interrupt and pm/fm generation process (inhibition function) ............................. 193 62. alarm interrupt hierarchy .................................................................................................. 197 63. ethermap-12 txc-04212 package diagram ..................................................................... 199 list of tables table page 1. configuration of rmaxdelvcg_x in low order vc .......................................................... 115 2. configuration of rmaxdelvcg_x in high order vc ......................................................... 115 3. scheduling matrix ........................................................................................................... ... 135 4. scheduling matrix mapped in the ethermap-12 register map .......................................... 136 5. latched alarm bit (l1alarm_name) transition selection .................................................. 186 6. latched alarm bit (l2alarm_name) transition selection .................................................. 189 - 7 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 features the ethermap-12 supports the following features. please note that the convention used in the transmit (or add) direction is from the ethernet line signal (smii/gmii) to the sdh/sonet format (telecom bus), while the receive (or drop) direction is from the sdh/sonet format to the ethernet line. general device level external sdram memory interface for: receive frame buffering for virtual concatenation delay compensation and ethernet flow control. transmit frame buffering with ethernet flow control. standard 16-bit wide microprocessor (lead selectable between motorola or intel mode). one second performance and fault monitoring registers/counters, with alarm and performance statistics generation. on-chip ethernet rmon statistics capability; as per rfc 2819. high and low order tributary poh interface. high and low order alarm indication port. smii/gmii ethernet interface for connection to phy ? s/mac ? s. ethernet management interface. byte wide add/drop telecom bus interface (77.76 mhz). power-up to a default configuration (with disabled telecom bus interface). sonet/sdh mappings: the mapper and demapper blocks provide the following rates and format mappings: sts-12c spe sts-12 / sts-9c spe sts-12 / sts-6c spe sts-12 / sts-3c spe sts-12 / sts-1 spe sts-12 / sts-1 / vt1.5 spe stm-4 / aug-4 / au-4-4c / vc-4-4c stm-4 / aug-4 / aug-1 / au-4 / vc-4 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tu-3 / vc-3 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-12s / vc-12 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-11s / vc-11 stm-4 / aug-4 / aug-1 / au-3 / vc-3 stm-4 / aug-4 / aug-1 / au-3 / vc-3 / tug-2 / tu-12 / vc-12 stm-4 / aug-4 / aug-1 / au-3 / vc-3 / tug-2 / tu-11 / vc-11 all supported mappings can be mixed according to the [g.707] multiplexing structure up to a total payload rate equivalent to one stm-4/sts-12 signal. - 8 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the mapper and demapper blocks provide mapping/demapping of gfp/laps/lapf/ppp/transparent hdlc frames into/from the following sonet/sdh structures: for low order sdh applications 1 , the frames are carried in, extracted from, vc-12s or vc-11s in the vc-4 structure using a tug-3 mapping scheme, or in the vc-3 structure using a tug-2 mapping scheme. complete low order poh will be generated resp. terminated. the k4/z7 byte is used for low order virtual concatenation. for low order sonet applications, the frames are carried in, extracted from, vt1.5s or vt2s in a sts-1 that is carried in a sts-12 structure. complete low order poh will be generated resp. terminated. the k4/z7 byte is used for low order virtual concatenation. for high order sdh applications, the frames are carried in, extracted from, vc-3s 1 using tug-3s with tu-3s, or in vc-4s or in a single vc-4-4c structure. complete high order poh will be generated resp. terminated.the h4 byte is used for high order virtual concatenation. for high order sonet applications, the frames are directly carried in, extracted from, sts-1 spes, or in sts-3c spes, or in a single sts-6c spe, or in a single sts-9c spe, or in a single sts-12c spe. complete high order poh will be generated resp. terminated.the h4 byte is used for high order virtual concatenation. sonet/sdh tx mapper high order path 1 the mapper complies to the latest itu/etsi/ansi standards and features regarding the generation of the high order path overhead bytes. these features include: j1 byte: 16 or 64 byte trail trace identifier. b3 byte: bip-8 calculation and insertion. c2 byte: signal label insertion. g1 byte: rei insertion (remote information from receive side). rdi insertion (remote information from receive side): single or three bit. optionally rdi generation for a minimum of 20 multiframes. h4 byte: optionally low order v1/v2 multiframe generation. optionally virtual concatenation multiframe generation. optionally lcas source state machine and control word generation. unequipped generation. supervisory unequipped generation. ais generation. tandem connection monitoring application is not supported. 1. note: in itu-t sdh a vc-3 can either be high order (au-3/sts-1) or low order (tu-3). in the remainder of the ether- map-12 data sheet high order and low order refers to the type of path overhead bytes rather than the order of the path in the multiplexing hierarchy. though both low and high order vc-3 mapping is supported, vc-3 operation will be covered in the high order path sections. - 9 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 low order path the mapper complies to the latest itu/etsi/ansi standards and features regarding the generation of the low order tu/vt path overhead bytes. these features include: j2 byte: 16 byte trail trace identifier. v5 and k4/z7 byte: rei insertion (remote information from receive side). rfi insertion: microprocessor control. bip-2 calculation and insertion. rdi insertion (remote information from receive side): single or three bit. optionally rdi generation for a minimum of 20 multiframes. (extended) signal label insertion. 32-bit virtual concatenation multiframe generation. optionally lcas source state machine and control word generation. unequipped generation. supervisory unequipped generation. ais generation. tandem connection monitoring application is not supported. sonet/sdh rx demapper high order path the rx demapper complies to the latest itu/etsi/ansi standards and features regarding the processing of the high order path overhead bytes. these features include: j1 byte: 16 or 64 byte trail trace identifier. b3 byte: bip-8 bit/block error counter option. c2 byte: signal label mismatch, unequipped, and vc ais detection. g1 byte: rdi detection, single or three bit. rei error counter. h4 byte: optionally low order v1/v2 multiframe monitoring. optionally virtual concatenation multiframe monitoring. optionally lcas sink state machine and control word retrieval. - 10 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 low order path the rx demapper complies to the latest itu/etsi/ansi standards and features regarding the processing of the low order path overhead bytes. these features include: j2 byte: 16 byte trail trace identifier. v5 and k4/z7 byte: rdi detection, single or three bit. rei error counter. rfi detection. bip-2 bit/block error counter option. signal label mismatch, unequipped, and vc ais detection. 32-bit virtual concatenation multiframe monitoring. optionally lcas sink state machine and control word retrieval. tandem connection monitoring application is not supported. virtual concatenation a maximum differential delay of 64 ms is supported using an external sdram memory module. in addition, support for lcas (link capacity adjustment scheme) is provided, based on the ansi t1.105-2001 and g.7042/y.1305 documents. the h4 and k4/z7 processing includes the virtual concatenation multiframe processing, along with the lcas control words to achieve hitless capacity adjustment. note on the lcas processing: there are configuration options that will make the h4 and k4/z7 byte processing compatible with non-lcas virtual concatenation systems. tx and rx eos processors the transmit and receive eos (ethernet over sonet/sdh) processor blocks support the following encapsulation standards: generic framing procedure (gfp). framed mode gfp, that will assume the following type of clients: 10/100/1000 mbps ethernet. link access procedure sdh (laps). ethernet over laps, itu-t x.86 (02/2001): for extension of lans (10/100/1000 mbps ethernet) over wan within a private and/or public network. link access procedure frame relay (lapf) point-to-point protocol (ppp) with bridging control protocol (bcp) and link control protocol (lcp) support. transparent hdlc processing (t.hdlc) each ethernet port allows the use of only one encapsulation standard at a time. however, the device can support simultaneous operation of all encapsulation standards across the ethernet ports. ethernet ports the ethermap-12 provides the following ethernet port features: eight independent smii (serial medial independent interfaces) for 10/100 mbit/s ethernet global 125 mhz reference clock global synchronization signal lead selects phy or switch connection to external client - 11 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 single gmii (gigabit mii) for 1000 mbit/s ethernet lead shared with the smii ports selection of gmii or smii is selected through a lead ethernet management interface phy or switch selection 10/100/1000 mbps ethernet mac blocks compliant to ieee 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac full duplex operation in 10/100/1000 mbit/s half duplex operation in 10/100 mbit/s mac control sub layer provides support for control frames including pause frames provides support for statistics gathering based on rmon mib group 1, rmon mib group 2, rmon mib group 3, rmon mib group 9, rmon mib 2, and the dot 3 ethernet mib gmii mux mode sdram interfaces glueless interface to external 256 mbits sdram devices 32 data, 13 address, 1 chip select, 1 clock, 1 clock enable, 1 row address strobe, 1 column address strobe, 1 write enable strobe, 1 data bus mask, and 2 bank address leads buffers tx/rx data transfers clock frequency of 125 mhz programmable refresh period cas latency of 3 supported refresh operation is transparent to the user (i.e. auto-refresh) microprocessor interface 17-bit address 16-bit data bus motorola or intel style split bus supported interrupt request lead interrupt mask bits for controlling generation of hardware interrupt requests jtag interface ieee 1149.1 compliant tap is provided for board level testing. device driver device configuration fault monitoring performance monitoring - 12 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 block diagram figure 1. functional block diagram of the ethermap-12 macs/rmon micro-processor interface clock generator operation control, jtag ref clocks drop telecom bus add telecom bus ethernet line side tx lo poh port ethernet management decapsulation frame deinterleave tx sdram controller encapsulation rx virtual concatenation and lcas virtual concatenation and lcas sdh/sonet side sonet/sdh low order demapper sonet/sdh low order mapper sonet/sdh low order cross connect sonet/sdh high order demapper tx lo alarm indication port tx ho poh port tx ho alarm indication port rx lo poh port rx lo alarm indication port rx ho poh port rx ho alarm indication port rx sdram controller sdram (rxfifo) (holfifo) sdram (txfifo) transmit path to rxfifo to holfifo receive path sonet/sdh high order mapper sonet/sdh high order cross connect 1 x gmii or 8 x smii - 13 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 block diagram description the ethermap-12 provides functionality for mapping and demapping of ethernet frames to and from sonet/sdh virtual concatenated tributary structures in both lcas/non-lcas mode. on the sonet/sdh side, the ethermap-12 supports a stm-4/sts-12/sts-12c like structure using a single transwitch defined telecom bus operating at 77.76 mhz. on the ethernet line side, the ethermap-12 supports either up to eight 10/100 mbps ethernet ports, or one 1000 mbps (gigabit) ethernet port. the eight 10/100 mpbs ethernet ports each support the industry standard smii interface. the single gigabit ethernet port supports the industry standard gmii interface. in the transmit direction (ethernet-to-sonet/sdh), the ethermap-12 terminates the 10/100/1000 mbps ethernet traffic. the ethernet frames from configured port(s) are extracted and buffered in the txfifo, which resides in external sdram memory. the txfifo is primarily used for implementing flow control when the ethernet line side bandwidth is greater than the allocated bandwidth on the sonet/sdh side (i.e., an over- subscription situation). based on system configuration, ethernet frames from each of the ethernet ports are encapsulated using one of the supported link layer protocols: laps, gfp, ppp, lapf or transparent hdlc. the encapsulated ethernet frames are byte interleaved over preselected sonet/sdh containers and transported using virtual concatenation. the ethermap-12 provides complete high and low order path overhead generation for the sonet/sdh containers. the bandwidth of sonet/sdh containers using virtual concatenation, are allowed to increase or decrease in a hitless fashion using the link capacity adjustment scheme (lcas). the sonet/sdh containers carrying ethernet frames are then be transmitted to an upstream sonet/sdh (line/section) overhead terminator device using a parallel telecom bus. in the receive direction (sonet/sdh-to-ethernet), the ethermap-12 terminates a parallel telecom bus with sonet/sdh containers carrying ethernet frames. the ethermap-12 provides complete high and low order path overhead processing for the sonet/sdh tributaries. the sonet/sdh containers are extracted and buffered in the rxfifo which resides in external sdram memory. the txfifo is used primarily for providing alignment and differential delay compensation for the selected sonet/sdh containers which form part of the virtual concatenation group. once alignment and delay compensation has been achieved, the ethernet frames are byte de-interleaved from the sonet/sdh containers to form their original frame structure on a per port basis. next, ethernet frames are extracted from the encapsulation frame (laps, gfp, ppp, lapf or transparent hdlc) and are buffered in the hol (head-of-line) fifo, which is in external sdram. the hol fifo buffers ethernet frames when periods of congestion are seen at the ethernet outputs. when congestion clears, frames are retrieved from the hol fifo and passed onto the ethernet port for transmission to the external client(s). the multiple ethermap software driver supports the ethermap-12 device and has the same architecture as other transwitch device drivers, and is meant to be easily integrated with them. the application software calls the driver functions to configure, control and manage the ethermap-12 device. the device driver insulates the application from the internal details of the device register usage and provides a higher level of abstraction. - 14 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ethermap-12 device interfaces the ethermap-12 provides the following main external interfaces. 10/100 mbps ethernet smii this interface is used to allow the ethermap-12 to connect to an external 10/100 mbps ethernet client (phy/switch). the ethermap-12 device supports eight independent smii interfaces. the smii interfaces are lead-shared with the gmii interface. the configuration choice is made during initialization/reset phase through a package signal lead. the smii interface is comprised of two signals per port, a global synchronous pulse signal and a global 125 mhz reference clock. all signals are synchronous to the clock. during initialization/reset phase, a package signal lead is used to allow selection between smii and gmii interfaces. furthermore, when using smii interface, another package signal lead is used to select the type of smii connection to external client: phy or switch. the state of the package leads will have a continuous effect on the selections. 1000 mbps ethernet gmii this interface is used to allow the mapper to connect to an external 1000 mbps ethernet client (phy/switch). the ethermap-12 device supports a single gmii interface. the gmii interface is lead-shared with the smii interfaces. the configuration choice is made on power-up/initialization through a package signal lead. the gmii interface is comprised of two independent rx and tx 8-bit data paths, two control signals per data path direction, two network status signals and a clock per data path direction. all signals are synchronous to their respective clocks. ethernet management interface this interface is used to connect an external ethernet phy to the ethermap-12 in order to configure and control its operation. the ethermap-12 device supports a single ethernet management interface. this interface is used by all of the eight 10/100 mbps ports or the single 1000 mbps port. the ethernet management interface is comprised of an output management data clock signal and a bidirectional management data signal that allows serial data to be clocked in and out of the external phy device. all data transfers are synchronous to the clock signal. this interface provides support for up to 32 phys. microprocessor interface this interface is used to allow the ethermap-12 to communicate with to an external microprocessor. the interface provides support for a standard motorola 68360/mpc860/mpc8260 or intel split address/data bus interface that allows access to the ethermap-12 memory map register locations. the mode of operation is configurable via external hardware signal leads. sdram memory interfaces these interfaces are used to allow the mapper to connect to two external sdram memory modules. the external sdram memory modules are used for buffering of ethernet traffic in both directions and also provides sonet/sdh frame storage for differential delay compensation. the sdram memory interface comprises of a 32-bit data bus, 13-bit address bus, bank address bus, 3-bit command bus, input/output mask bus, system clock (up to 125 mhz) and control enable signals. this interface provides a "glueless" interface to the 256 mbits sdram memory modules. - 15 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parallel line side telecom bus interface this interface is used to allow the ethermap-12 to connect to an upstream sonet/sdh line overhead terminator using a parallel telecom bus interface. this interface is collectively comprised of a single drop and a single add bus. the drop bus is composed of a 8-bit wide input data bus, a byte clock input (77.76 mhz), a payload timing input signal, a payload active input signal and a parity indication input signal. the add bus is composed of a 8-bit wide output data bus, a byte clock input/output (77.76 mhz), a payload timing input/output signal, a payload active input/output signal, a parity indication output signal and an add bus active indicator output signal. the ethermap-12 provides support for add bus timing modes. high & low order poh port interface the poh byte interface provides an alternative access to all of the sonet/sdh low order and high order tributary poh bytes for external processing. there are two separate poh byte interfaces, one for low order (vt1.5/vc-12) poh, and one for high order (sts-1/vc-3, sts-3c/vc-4, sts-6c, sts-9c, and sts-12c/vc- 4-4c) poh. individual poh byes except j1/j2, c2/v5/k4 signal label and bip-2/bip-8 fields are inserted into the poh from the transmit poh byte interface. all poh bytes are provided at the receive poh byte interface for external processing. high & low order alarm indication port interface the alarm indication port is provided to transport the remote information signal from a mate poh monitor to the poh generator. the remote information includes rei, rdi and various extended rdi indications. there are two separate alarm indication ports, one for low order (vt1.5/vc-12) remote information, and one for high order (sts-1/vc-3, sts-3c/vc-4, sts-6c, sts-9c, and sts-12c/vc-4-4c) remote information. jtag interface this interface provides a five signal boundary scan capability that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test. in addition to the tap, a lead is provided to place the output buffers in a high impedance state for systems that do not support the ieee 1149.1 standard. - 16 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ethernet over sonet sdh mapping the ethermap-12 device supports mapping of ethernet frames over sonet/sdh containers using the mappings shown in figure 2 . figure 2. mapping of ethernet frames over sonet/sdh vt1.5-xc payload c-11-xc vt2-xc payload c-12-xc sts-1-xc payload c-3-xc aug-1 tug-3 tug-2 sts-12c spe vc-4-4c au-4 sts-3c au-3 sts-1 tu-3 tu-12 vt2 tu-11 vt1.5 au-4-4c sts-12c sts-9c sts-6c sts-3c spe vc-4 sts-1 spe vc-3 sts-6c spe sts-9c spe vt2 spe vc-12 vt1.5 spe vc-11 vc-3 vt1.5 payload c-11 vt2 payload c-12 sts-1 payload c-3 sts-3c payload c-4 sts-12c payload c-4-4c sts-6c payload sts-9c payload x1 x2 x1 x4 x3 x7 x3 x4 x1 aug-4 x3 x7 x1 sts-3c-xc payload c-4-xc 1/x 1/x 1/x 1/x x=4 x=2 x=3 encapsulated ethernet frames vt group sonet sdh multiplexing mapping aligning 1/x virtual concatenation pointer processing - 17 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 data processing/flow the ethermap-12 provides functionality for mapping and demapping of ethernet frames to and from sonet/sdh virtual concatenated tributary structures. figures 3 and 4 represent the virtual tributary structures that are supported by the ethermap-12 device. figure 3 shows the vc-11-xv/vc-12xv/vt1.5-xv/vt2-xv structure. the vcg provides a payload area of x times the payload capacity of the corresponding low order path container. the payload is mapped in the payload area of x individual low order path containers which form the members of the vcg. each low order path container has its own poh. figure 3. low order virtual concatenation structure for sonet v5 j2 1 1 26 vc-11/vt1.5 spe #x 1 1 4 x x x 25 v5 j2 n2 k4 1 4 1 c-11-xc/vt1.5-xc spe vc-11/vt1.5 spe #1 500 s 500 s vc-11-xv/ payload capacity x x 34 c-12-xc/vt2-xc spe payload capacity vc-12/vt2 spe #x vc-12/vt2 spe #1 vt1.5-xv spe vc-12-xv/ vt2-xv spe 35 - 18 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 4 shows the vc-3-xv/vc-4-xv/sts-1-xv/sts-3c-xv structure. the vcg provides a payload area of x times the payload capacity of the corresponding high order path container. the payload is mapped in the payload area of x individual high order path containers which form the members of the vcg. each high order path container has its own poh. figure 4. high order virtual concatenation structure for sonet/sdh j1 b3 1 1 85 vc-3/sts-1 spe #x 1 1 9 x x x 84 j1 b3 c2 g1 1 9 1 c-3-xc/sts-1-xc spe vc-3/sts-1 spe #1 125 s 125 s vc-3-xv/ n1 k3 f2 f3 h4 125 s sts-1-xv spe payload capacity vc-4/sts-3c spe #1 vc-4/sts-3c spe #x x x 260 c-4-xc/sts-3c-xc spe payload capacity 261 sts-3c-xv spe vc-4-xv/ - 19 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 5 shows the vc-4-xc/sts-nc (n = 3x) contiguous concatenated structure. the contiguous concatenated container provides a single poh column, (x-1) stuff columns, and a payload area of x times the payload capacity of the vc-4/sts-3c high order path container. figure 5. vc-4-xc/sts-nc (n = 3x) contiguous concatenation structure for sonet/sdh 1 1 9 x 125 s x x 260 c-4-xc/sts-3c-xc spe payload capacity x+1 j1 b3 c2 g1 n1 k3 f2 f3 h4 x x 261 (x-1) fixed stuff column - 20 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 application examples phast ? -12n txc-06312 4 x oc-3/stm-1 or oc-12/stm-4 8 x 10/100 mbps smii ports or 1 x gmii ports vc-3/vc-4 cross-connect vc-3/vc-4 and/or vc-11/vc-12 cross-connects sdram 77.76 mhz telecom bus 16 x 10/100 ethermap-12 txc-04212 sdram switch (24) ethernet clients - 21 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 lead diagram figure 6. ethermap-12 txc-04212 lead diagram bottom view a b c d e f g h j k l m n p r t u v w y aa ab ac ad af ae a b c d e f g h j k l m n p r t u v w y aa ab ac af ae ad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 6 - 22 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 lead descriptions power supply, ground, and no connect leads symbol lead no. i/o/p* name/function vdd33 d4, d23, e5, e13, e14, e22, f6, f9, f10, f13, f14, f17, f18, f21, j6, j21, k6, k21, n5, n6, n21, n22, p5, p6, p21, p22, u6, u21, v6, v21, aa6, aa9, aa10, aa13, aa14, aa17, aa18, aa21, ab5, ab13, ab14, ab22, ac4, ac23 p vdd33: +3.3 volt power supply, 5%. vdd12 f7, f8, f11, f12, f15, f16, f19, f20, g6, g21, h6, h21, l6, l21, m6, m21, r6, r21, t6, t21, w6, w21, y6, y21, aa7, aa8, aa11, aa12, aa15, aa16, aa19, aa20 p vdd12: +1.2 volt power supply, 5%. vss a1, a2, a3, a24, a25, a26, b1, b2, b3, b24, b25, b26, c1, c2, c3, c24, c25, c26, j9, j10, j11, j12, j13, j14, j15, j16, j17, j18, k9, k10, k11, k12, k13, k14, k15, k16, k17, k18, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, m9, m10, m11, m12, m13, m14, m15, m16, m17, m18, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, p9, p10, p11, p12, p13, p14, p15, p16, p17, p18, r9, r10, r11, r12, r13, r14, r15, r16, r17, r18, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, u9, u10, u11, u12, u13, u14, u15, u16, u17, u18, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, ad1, ad2, ad3, ad24, ad25, ad26, ae1, ae2, ae3, ae24, ae25, ae26, af1, af2, af3, af24, af25, af26 p ground: 0 (zero) volts reference. vddp12 ac24 p vddp12: +1.2 volt digital power supply for the pll, 5%. vddp33 ab24 p vddp33: +3.3 volt digital power supply for the pll, 5%. vddpa12 y22 p vddpa12: +1.2 volt analog power supply for the pll, 5%. vssp12 ab23 p vssp12: digital ground for the pll. vssp33 ac25 p vddp33: +3.3 volt digital power supply for the pll, 5% vsspa12 aa23 p vsspa12: analog ground for the pll. nc a11, a14, a19, a22, b7, b15, b17, c9, d6, d22, e6, e7, e10, e12, e16, e19, e21, e23, f5, f26, g4, g5, h23, j3, j5, j26, k3, k5, k24, m1, n24, n25, r5, t22, u24, w1, w4, w5, w22, y3, aa2, aa5, aa22, ab6, ab26, ac5, ac17, ac22, ad7, ad10, ae7, ae13, ae18, af4, af6, af9, af13 no connect: these leads are not to be connected, not even to another no connect lead, and must be left floating. connection of an nc lead may impair performance or cause damage to the device. nc leads that are currently unused may be assigned functions in a future version of the device, affecting its usability in applications which have not left them floating. * note: i = input; o = output; od=open drain output; p = power; t = tristate: - 23 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 line side drop telecom bus interface symbol lead no. i/o/p type name/function tbdd7 tbdd6 tbdd5 tbdd4 tbdd3 tbdd2 tbdd1 tbdd0 c15 d15 e15 a16 b16 c16 d16 a17 i lvttl-5 drop bus data in: byte wide data corresponding to the stm-4/sts-12 rate signal from the drop bus. the first bit received (dropped) corresponds to bit 7. tbdclk a15 i lvttl-5 drop bus clock: this clock operates at 77.76 mhz for stm- 4/sts-12 operation and is used to clock data and other signals into the ethermap-12. drop bus byte wide data, the parity bit, spe indication, and the c1j1v1 signals are clocked into the ethermap-12 on negative transitions of this clock. tbdc1j1v1 d14 i lvttl-5 drop bus spe indicator/multiframe pulse: an active high timing signal that carries frame and spe information. this signal works in conjunction with the tbdspe signal. the single c1 pulse identifies the location of the first c1 byte when tbdspe signal is low. one j1 pulse per sts/au identifies the starting location of the j1 bytes in the stm-4/sts- 12 signal when tbdspe is high. one v1 pulse per substructured sts/au identifies the v1/v2 multiframe. the j1 pulse is optional in the tbdc1j1v1 signal. the ethermap-12 provides pointer tracking. the v1 pulse is optional in the tbdc1j1v1 signal. the ethermap-12 also provides h4 detectors to determine the location of the v1/v2 bytes in place of using the v1 pulse. tbdspe c14 i lvttl-5 drop bus spe indicator: a signal that is active high during each byte of the stm-4/sts-12 poh and payload bytes, and low during transport overhead byte times. tbdpar b14 i lvttl-5 drop bus parity bit: parity bit input signal that represents the parity calculation for each data byte, spe, and c1j1v1 signal from the bus. even or odd parity may be detected, and an option for the data byte only is provided. a parity error has no effect of the operation of the ethermap-12. a control bit is provided that allows even or odd parity to be detected. - 24 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 line side add telecom bus interface symbol lead no. i/o/p type name/function tbad7 tbad6 tbad5 tbad4 tbad3 tbad2 tbad1 tbad0 d11 c11 b11 d12 c12 b12 a12 d13 o(t) lvcmos 16 ma add bus data byte out: byte wide data that corresponds to the selected tu/vt/vc. the first bit transmitted (added) corresponds to bit 7. tbac1j1v1 b10 i/o* lvttl-5/ lv c m o s 16 ma add bus spe indicator/multiframe pulse: composite active high input timing signal that carries stm-4 or sts-12 starting frame, and j1 byte location information. this timing signal functions in conjunction with the tbaspe signal. the c1(j0) pulse identifies the location of the first c1(j0) byte in the sonet/sdh frame when tbaspe is low. a j1 pulse identifies the starting location of each j1 byte in the constituent vc-4 signal or three j1 pulses identify the starting location of the twelve j1 bytes for the sts-1 signals in the sts-12 signal when tbaspe is high. one or more v1 pulses may be present for asynchronous vt/tu mappings to determine the starting location of the v1 byte. this signal is active high during each byte of the stm-4/sts-12 payload, and low during transport overhead times. tbaspe e11 i/o* lvttl-5/ lv c m o s 16 ma add bus spe indicator: this signal is active high during each byte of the poh and payload bytes, and low during transport overhead times. tbapar c10 o(t) lvcmos 16 ma add bus parity signal: an odd or even parity output signal which is calculated over the byte wide add data. this 3-state lead is only active when there is data being added to the add bus. a control bit is provided that allows even or odd parity to be calculated. tbadd a9 o lvcmos 16 ma add bus add data present indicator: this normally active low signal is present when output data to the add bus is valid. it identifies the location of all of the tu/vt time slots being selected. a control bit is provided that allows this bit to be active high. * when tbmaster =0 and tbmode =1, these signals are output by the device for source timing, in all other cases these signals must be input for add bus timing. - 25 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ethernet gmii/ 8xsmii interfaces the control lead, gmii/smii , when low, selects the group of eight smii ethernet interfaces, and when high, selects the single gmii interface. the gmii interface is described in the section below, and also how the leads are shared with the smii interface leads. each smii interface is comprised of a 125 mhz serial transmit data output (smii_don) and serial receive data input (smii_din); where n = 1 to 8. symbol lead no. i/o/p type name/function etntxgclk ac8 o lvcmos 12 ma gigabit ethernet transmit clock output: in gmii mode, this lead is used to output a 125mhz clock (i.e., to a phy device). the etntxd[7-0] , etntxen and etntxer signals are synchronously driven with this clock. in smii mode, this clock should not be used. etntxclk af7 i lvttl-5 gmii transmit clock: in gmii mode, this lead is used, alternatively, to input a 125mhz clock (i.e., either from a phy device or an external system clock source), to be used for the gmii transmit side datapath signals such as etntxd[7-0] , etntxen and etntxer. in smii mode, this input is not used. etntxen ae8 i/o lvttl-5/ lv c m o s 12 ma gmii transmit enable/global smii sync: in gmii mode, this lead is used to output a control signal to indicate valid data is being presented on the etntxd[7-0] . in smii mode and when connected to a phy device (or a switch), this lead is used to output a global sync signal (i.e., common for all eight smii interfaces). in smii mode and when connected to a switch device (i.e., a mac-mac connection), this lead is used to input a global sync signal (i.e., common for all eight smii interfaces). etntxer ab9 o lvcmos 8 ma gmii transmit error: in gmii mode, this lead is used to output a control signal to indicate that a coding violation was received on the input data stream. in smii mode, this input lead is not used. etntxd7 etntxd6 etntxd5 etntxd4 etntxd3 etntxd2 etntxd1 etntxd0 ae10 af8 ae9 ab10 ac10 ad9 ad8 ac9 olvcmos 12 ma gmii/smii transmit data out: in gmii mode, these leads are used to output the byte wide data (i.e., to a phy device). in smii mode, each of the eight leads is used to output an independent serial data stream for the corresponding smii interface. etnrxd7 etnrxd6 etnrxd5 etnrxd4 etnrxd3 etnrxd2 etnrxd1 etnrxd0 ac12 ab12 ad12 af11 ad11 ac11 ab11 af10 i lvttl-5 gmii/smii receive data in: in gmii mode, these leads are used to input the byte wide data (i.e., from a phy device). in smii mode, each of the eight leads is used to input an independent serial data stream for the corresponding smii interface. - 26 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 etnrxdv ae11 i lvttl-5 gmi receive data valid: in gmii mode, this lead is used as an input to indicate valid data is present on the etnrxd[7-0] . in smii mode, this lead is not used. etnrxer ae12 i lvttl-5 gmii receive data error: in gmii mode, this lead is used to input a control signal to indicate that a frame has been received in error. in smii mode, this lead is not used. etnrxclk af12 i lvttl gmii/smii receive clock: in gmii mode, this lead is used to input a 125mhz clock (i.e., from a phy device), to be used for the gmii receive side datapath signals such as etnrxd[7-0] , etnrxdv and etnrxer. in smii mode, this lead is used to input a global 125mhz clock signal (i.e., common for all eight smii interfaces). etnmdio ac13 i/o lvttl-5 /lvcmos 8 ma mii management data i/o: this is a bidirectional lead that is used for serial data to be clocked in or out of an external phy device. serial data is clocked out synchronously with the clock etnmdc lead. (data input/output for the ieee 802.3u compliant management and status.) this lead is used in both gmii and smii modes. etnmdc ad13 o lvcmos 8 ma mii management data interface clock: this lead will output a clock of 2.5mhz used to synchronously transfer data in and out of an external phy device using the etnmdio lead. symbol lead no. i/o/p type name/function - 27 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 sdram interface 1 symbol lead no. i/o/p type name/function sd1d31 sd1d30 sd1d29 sd1d28 sd1d27 sd1d26 sd1d25 sd1d24 sd1d23 sd1d22 sd1d21 sd1d20 sd1d19 sd1d18 sd1d17 sd1d16 sd1d15 sd1d14 sd1d13 sd1d12 sd1d11 sd1d10 sd1d09 sd1d08 sd1d07 sd1d06 sd1d05 sd1d04 sd1d03 sd1d02 sd1d01 sd1d00 t4 u3 u1 u2 t2 r4 t3 t1 r2 r3 r1 p3 p4 n2 p1 p2 n4 n1 n3 m5 m4 m2 m3 l1 l4 l2 k1 l3 l5 k2 k4 j1 i/o(t) lvttl/lv3 cmos 16 ma sdram data bus: 32 bits wide data bus; byte wise tri-stateable. sd1a12 sd1a11 sd1a10 sd1a09 sd1a08 sd1a07 sd1a06 sd1a05 sd1a04 sd1a03 sd1a02 sd1a01 sd1a00 y4 aa3 v4 aa1 v5 w3 y1 w2 y2 v3 u5 u4 v2 olv3cmos 16 ma sdram address bus: 13 bits wide address bus. - 28 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 sd1ba1 sd1ba0 y5 ab1 olv3cmos 16 ma bank select: these signals are used to select the banks of a standard sdram device. sd1ras ab2 o lv3cmos 16 ma row address strobe: for control of external sdram. this signal along with sd1cas and sd1we define the command being given to the external sdram. sd1cas aa4 o lv3cmos 16 ma column address strobe: for control of external sdram. his signal along with sd1we and sd1ras define the command being given to the external sdram. refer to the table in the sd1ras lead description. sd1we ab4 o lv3cmos 16 ma write enable: for control of external sdram. this signal along with sd1cas and sd1ras define the command being given to the external sdram. refer to the table in the sd1ras lead description. sd1cs2 sd1cs1 ac1 ab3 olv3cmos 16 ma chip select: for control of external sdram. used to select and deselect external sdram. sd1mask ac2 o lvcmos 16 ma mask bits: this control output is used to mask out the standard 32 bit wide sdram memory interface. it is used to tristate the sdram data bus during a read cycle and to mask the sdram data bus during a write cycle. sd1clka v1 o lv3cmos 16 ma interface clock: for control of external sdram. all sdram interface signals are sampled/output on the rising edge of this clock, which runs at 125 mhz. symbol lead no. i/o/p type name/function ras cas we function 111 nop: no operation 01 1 active: used to activate a row in a particular bank. the sd1ba(1-0) selects the bank, and sd1a (12-0) selects the row. 101 read: used to initialize the sdram for a burst read. 100 write: used to initialize the sdram for a burst write. 010 precharge: deactivate open row in a bank or banks. 001 auto refresh: this command is per- formed every 1240 sysclk period, to ensure that all of the sdram rows are refreshed. this default setting can be changed by sdrarp at register address tbd. 000 load mode register: this command is issued at the end of the configuration step, to configure the internal mode register of the sdram. it is the last command before the sdram to be ready for read/write accesses. - 29 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 sdram interface 2 sd1clkb t5 i lvttl-5 interface clock input: for control of external sdram. this input must be connected externally to sd2clka output. sd1clke ac3 o lv3cmos 16 ma interface clock enable: for control of external sdram. high is intended to activate the clock, low is intended to deactivate the clock. symbol lead no. i/o/p type name/function sd2d31 sd2d30 sd2d29 sd2d28 sd2d27 sd2d26 sd2d25 sd2d24 sd2d23 sd2d22 sd2d21 sd2d20 sd2d19 sd2d18 sd2d17 sd2d16 sd2d15 sd2d14 sd2d13 sd2d12 sd2d11 sd2d10 sd2d09 sd2d08 sd2d07 sd2d06 sd2d05 sd2d04 sd2d03 sd2d02 sd2d01 sd2d00 n26 p26 p25 p24 p23 r26 r25 r24 r23 r22 t26 t25 t24 t23 u26 u25 v26 u23 v25 u22 v24 w26 w25 v23 y26 w24 v22 y25 aa26 w23 y24 aa25 i/o(t) lvttl/lv cmos 16 ma sdram data bus: 32 bits wide data bus; byte wise tri- stateable. symbol lead no. i/o/p type name/function - 30 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 sd2a12 sd2a11 sd2a10 sd2a09 sd2a08 sd2a07 sd2a06 sd2a05 sd2a04 sd2a03 sd2a02 sd2a01 sd2a00 k25 h25 l23 j25 l22 m22 m23 l24 k26 l25 m24 n23 l26 olvcmos 16 ma sdram address bus: 13 bits wide address bus. sd2ba1 sd2ba0 k23 k22 olvcmos 16 ma bank select: these signals are used to select the banks of a standard sdram device. sd2ras j24 o lvcmos 16 ma row address strobe: for control of external sdram. this signal along with sd2cas and sd2we define the command being given to the external sdram. sd2cas h24 o lvcmos 16 ma column address strobe: for control of external sdram. his signal along with sd2we and sd2ras define the command being given to the external sdram. refer to the table in the sd2ras lead description. symbol lead no. i/o/p type name/function ras cas we function 111 nop: no operation 01 1 active: used to activate a row in a particular bank. the sd2ba(1-0) selects the bank, and sd2a(12-0) selects the row. 101 read: used to initialize the sdram for a burst read. 100 write: used to initialize the sdram for a burst write. 010 precharge: deactivate open row in a bank or banks. 001 auto refresh: this command is per- formed every 1240 sysclk period, to ensure that all of the sdram rows are refreshed. this default setting can be changed by sdrarp at register address tbd. 000 load mode register: this command is issued at the end of the configuration step, to configure the internal mode register of the sdram. it is the last command before the sdram to be ready for read/write accesses. - 31 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 receive ho path overhead (hopoh) byte interface sd2we j22 o lvcmos 16 ma write enable: for control of external sdram. this signal along with sd2cas and sd2ras define the command being given to the external sdram. refer to the table in the sd2ras lead description. sd2cs2 sd2cs1 h26 j23 olvcmos 16 ma chip select: for control of external sdram. used to select and deselect external sdram. sd2mask g26 o lvcmos 16 ma mask bits: this control output is used to mask out the standard 32 bit wide sdram memory interface. it is used to tristate the sdram data bus during a read cycle and to mask the sdram data bus during a write cycle. sd2clka m25 o lvcmos 16 ma interface clock: for control of external sdram. all sdram interface signals are sampled/output on the rising edge of this clock, which runs at 125 mhz. sd2clkb m26 i lvttl interface clock input: for control of external sdram. this input must be connected externally to sd2clka output. sd2clke g25 o lvcmos 16 ma interface clock enable: for control of external sdram. high is intended to activate the clock, low is intended to deactivate the clock. symbol lead no. i/o/p type name/function pohrxclk b21 o lvcmos 12 ma receive hopoh interface clock: the receive hopoh address (pohrxpadd), address latch enable (pohrxale), data (pohrxdat), and data latch enable (pohrxdle) signals are clocked out on falling edges of this clock (77.76 mhz). pohrxale c20 o lvcmos 8 ma receive hopoh interface address latch enable: a positive 8 (pohrxclk) clock cycle-wide pulse that indicates a valid address (eight consecutive bits) present on pohrxadd. pohrxadd a21 o lvcmos 8 ma receive hopoh interface address: the states present on these leads during address latch enable time indicate the output hopoh byte and the sdh/sonet format. eight consecutive bits make up a valid address. pohrxdle d19 o lvcmos 8 ma receive hopoh interface data latch enable: a positive 8 (pohrxclk) clock cycle-wide pulse that indicates valid data present on pohrxdat. pohrxdat b20 o lvcmos 8 ma receive hopoh interface data: the states present on these leads over eight consecutive bits, during data latch enable time constitute the output byte data selected by the address. symbol lead no. i/o/p type name/function - 32 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 transmit ho path overhead (hopoh) byte interface receive lower order path overhead (lopoh) byte interface symbol lead no. i/o/p type name/function pohtxclk d8 o lvcmos 12 ma transmit hopoh interface clock: the transmit poh address (pohtxadd), address latch enable (pohtxale), and data latch enable (pohtxdle) signals are clocked out on falling edge of pohtxclk (77.76 mhz). data (pohtxdat), is clocked in. pohtxale a6 o lvcmos 8 ma transmit hopoh interface address latch enable: a positive 8 (pohtxclk) clock cycle-wide pulse that indicates a valid address (eight consecutive bits) present on pohtxadd. pohtxadd c7 o lvcmos 8 ma transmit hopoh interface address: the states present on this lead during address latch enable time indicate the output poh byte and the sdh/sonet format. eight consecutive bits make up a valid address. pohtxdle b6 o lvcmos 8 ma transmit hopoh interface data latch enable: a positive 8 (pohtxclk) clock cycle-wide pulse that indicates valid data present on pohtxdat pohtxdat e8 i lvttl-5 transmit hopoh interface data: the states present on these leads over eight consecutive bits, during data latch enable time, constitute the input byte data selected by the address. symbol lead no. i/o/p type name/function pohrxclk1 e18 o lvcmos 12 ma receive lopoh interface clock: the receive lopoh address (pohrxadd1), address latch enable (pohrxale1), data (pohrxdat1), and data latch enable (pohrxdle1) signals are clocked out on falling edges of this clock (77.76 mhz). pohrxale1 c19 o lvcmos 8 ma receive lopoh interface address latch enable: a positive 12 (pohrxclk1) clock cycle-wide pulse that indicates a valid address (twelve consecutive bits) present on pohrxadd1. pohrxadd1 a20 o lvcmos 8 ma receive lopoh interface address: the states present on these leads during address latch enable time indicate the output lopoh byte and the sonet/sdh format. twelve consecutive bits make up a valid address. pohrxdle1 b19 o lvcmos 8 ma receive lopoh interface data latch enable: a positive 8 (pohrxclk1) clock cycle-wide pulse that indicates valid data present on rpdat1. pohrxdat1 d18 o lvcmos 8 ma receive lopoh interface data: the states present on these leads over eight consecutive bits, during data latch enable time constitute the output byte data selected by the address. - 33 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 transmit lower order path overhead (lopoh) byte interface receive (ho) high order alarm indication port transmit (ho) high order alarm indication port symbol lead no. i/o/p type name/function pohtxclk1 a5 o lvcmos 12 ma transmit lopoh interface clock: the transmit lopoh address (pohtxadd1), address latch enable (pohtxale1), and data latch enable (pohtxdle1) signals are clocked out on falling edge of pohtxclk1 (77.76 mhz). data (pohtxdat1), is clocked in. pohtxale1 c6 o lvcmos 8 ma transmit lopoh interface address latch enable: a positive 12 (pohtxclk1) clock cycle-wide pulse that indicates a valid address (twelve consecutive bits) present on pohtxadd1. pohtxadd1 d7 o lvcmos 8 ma transmit lopoh interface address: the states present on this lead during address latch enable time indicate the output lopoh byte and the sonet/sdh format. twelve consecutive bits make up a valid address. pohtxdle1 b5 o lvcmos 8 ma transmit lopoh interface data latch enable: a positive 8 (pohtxclk1) clock cycle-wide pulse that indicates valid data present on pohtxdat1. pohtxdat1 a4 i lvttl-5 transmit lopoh interface data: the states present on these leads over eight consecutive bits, during data latch enable time, constitute the input byte data selected by the address. symbol lead no. i/o/p type name/function ringrxipf c18 o lvcmos 8 ma receive ho alarm indication port frame pulse: a active high one (ringrxipc) clock cycle-wide frame pulse that identifies bit 1 in the data stream. ringrxipc e17 o lvcmos 8 ma receive ho alarm indication port clock: a 77.76 mhz output clock used for clocking the frame pulse (ringrxipf) and the serial data (ringrxipd). ringrxipd b18 o lvcmos 8 ma receive ho alarm indication port data: a serial frame that contains the rei count and rdi alarm states for the high order paths. the rei count is converted to a four bit count. one byte per channel (24 channels) are needed. symbol lead no. i/o/p type name/function ringtxipf a8 i lvttl-5 transmit ho alarm indication port frame pulse: a active high one (ringtxipc) clock cycle-wide frame pulse that identifies bit 1 in the data stream. ringtxipc b8 i lvttl-5 transmit ho alarm indication port clock: a 77.76 mhz output clock used for clocking in the frame pulse (ringtxipf) and the serial data (ringtxipd). - 34 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 receive lo order alarm indication port transmit low order alarm indication port controls ringtxipd d9 i lvttl-5 transmit ho alarm indication port data: a serial frame that contains the rei count, rdi alarm states, and the tandem connection monitoring and alarm states for the individual high order paths. symbol lead no. i/o/p type name/function ringrxipf1 d17 o lvcmos 8 ma receive lo alarm indication port frame pulse: a active high one (ringrxipc1=19.44) clock cycle-wide frame pulse that identifies bit 1 in the data stream. ringrxipc1 a18 o lvcmos 8 ma receive lo alarm indication port clock: a 77.76 mhz output clock used for clocking in the frame pulse (ringrxipf1) and the serial data (ringrxipd1). ringrxipd1 c17 lvcmos 8 ma receive lo alarm indication port data: a serial frame that contains the rei count, rdi alarm states for the vt/tus. symbol lead no. i/o/p type name/function ringtxipf1 a7 i lvttl-5 transmit lo alarm indication port frame pulse: a active high one (ringtxipc1) clock cycle-wide frame pulse that identifies bit 1 in the data stream. ringtxipc1 c8 i lvttl-5 transmit lo alarm indication port clock: a 77.76 mhz output clock used for clocking in the frame pulse (ringtxipf1) and the serial data (ringtxipd1). ringtxipd1 e9 i lvttl-5 transmit lo alarm indication port data: a serial frame that contains the rei count, rdi alarm states, and the tandem connection monitoring and alarm states for the individual lo vt/tu paths. symbol lead no. i/o/p type name/function gmii/smii ad6 i lvttl-5p gmii/smii interface select: when low, the eight smii interfaces are selected. when high, the single gmii interface is selected. this lead must be held in the steady state during initialization/reset phase. this lead has an internal pull-up resistor. devhiz ac7 i lvttl-5p high impedance select: a low forces all output leads, except for the boundary scan data output tbdo, to the high impedance state for testing purposes. this lead has an internal pull-up resistor. symbol lead no. i/o/p type name/function - 35 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 clock interfaces reset ab8 i lvttl-5p reset: an active low signal used for resetting the internal cores/blocks and performance counters within the ethermap-12 to preset values. the reset must be applied only after power is applied and stable, and the clocks are also stable. the reset must be present for a minimum of 250 ns. this lead has an internal pull-up resistor. phy/mac ae6 i lvttl-5p phy/mac interface select: in smii mode and when low, the ethermap-12 device is connected to a mac (i.e., a switch). in smii mode and when high, the ethermap-12 device is connected to a phy device. in gmii mode and when high, the ethermap-12 device will use the gmii rx_clk (of 125mhz) to drive the gmii transmit side and output onto gtx_clk (entrxclk lead) lead (i.e., etntxgclk lead). in gmii mode and when low, the ethermap-12 device will use the tx_clk (etntxclk lead) to drive the gmii transmit side and output onto gtx_clk lead. this lead has an internal pull-up resistor. etnsyncdir af14 i lvttl-5p smii global sync direction select: in smii mode and when low, the smii_gsync signal (etntxen lead) is an input. in smii mode and when high, the smii_gsync signal will be an output. in gmii mode, this lead is not used. this lead has an internal pull-up resistor. tbmode b9 i lvttl-5 tbmode: selection of the mode of the line telecom bus. 0 means add slave, 1 means add master. tbmaster d10 i lvttl-5d tbmaster: selection of the mode of the line telecom bus. 0 means selection of the mode with tbmode. 1 means add master with tbac1j1v1 and tbaspe in tristate (independently from the value of tbmode). symbol lead no. i/o/p type name/function rtclk a10 i lvttl-5d sonet/sdh reference clock: this clock is a 77.76 mhz +/- 20 ppm reference clock used by the sonet/sdh blocks. rtfs a13 i lvttl-5d sonet/sdh reference frame sync: a 8 khz reference frame sync pulse synchronous to rtclk. rtmfs c13 i lvttl-5d sonet/sdh reference multiframe sync: a 2khz reference frame sync pulse synchronous to rtclk (and rtfs, if present). sysclk ab21 i cmos system reference clock: a 50 mhz input clock for all blocks except the sonet/sdh blocks. onesec b13 i lvttl-5d one second performance measurement clock: a 1.0 hz +/- 32 ppm clock used for the one second shadow counters, and pm/fm alarm registers. symbol lead no. i/o/p type name/function - 36 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 host processor interface selection note: all host processor interface modes share the same leads. generic intel - host processor interface symbol lead no. i/o/p type name/function mpmode1 mpmode0 ae23 ad22 i lvttl microprocessor interface select: these leads select the host processor interface mode: symbol lead no. i/o/p type name/function mpclk ad23 i lvttl microprocessor interface clock: this lead is the clock sourced by the microprocessor being interfaced to this device. its max. frequency is 50 mhz. intel notation: clk mpa16 mpa15 mpa14 mpa13 mpa12 mpa11 mpa10 mpa09 mpa08 mpa07 mpa06 mpa05 mpa04 mpa03 mpa02 mpa01 mpa00 af18 ad17 ae17 ab16 af17 ac16 ad16 ae16 af16 ab15 ac15 ad15 ae15 af15 ac14 ad14 ae14 ilvttl address bus: these leads are the address bus used by the host processor for accessing the ethermap-12 for a read or write cycle. mpa16 is the most significant bit in the location ? s address. intel notation: a[ ] mpmode1 mpmode0 interface 0 0 generic intel 0 1 generic motorola 1 0 motorola mpc860 1 1 motorola mpc8260 local bus - 37 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 generic motorola - host processor interface mpd15 mpd14 mpd13 mpd12 mpd11 mpd10 mpd09 mpd08 mpd07 mpd06 mpd05 mpd04 mpd03 mpd02 mpd01 mpd00 ac20 af22 ab19 ae21 ad20 af21 ac19 ae20 ab18 ad19 af20 ac18 ae19 af19 ad18 ab17 i/o(t) lvttl/ lv c m o s 8ma data bus: these leads are the bidirectional data bus used for transferring data between the ethermap-12 and the host proc- essor. mpd15 is the most significant bit. intel notation: d[ ] mpsel ad21 i lvttl ethermap-12 chip select (active low): this active low lead enables data transfers between the host processor and the ethermap-12 through a read or write cycle. intel notation: cs mpts ae22 i lvttl read strobe (active low): this active low lead initiates a read transfer between the host processor and the ethermap-12. intel notation: rd mpwr af23 i lvttl write strobe (active low): this active low lead initiates a write transfer between the host processor and the ethermap-12. intel notation: wr mpack ab20 o(t) lvcmos 24ma ready (active low): for a write access, an active edge on this lead indicates that data is written to the addressed memory location. for a read access, an active edge on this lead indi- cates that the data to be read from the addressed memory loca- tion is available on the data bus. intel notation: rdy mpintr ac21 o lvcmos 8ma interrupt (active high): this lead signals an interrupt request to the host processor. symbol lead no. i/o/p type name/function mpclk ad23 i lvttl microprocessor clock: this lead is the clock sourced by the microprocessor being interfaced to this device. its max. frequency is 50 mhz. motorola notation: clk symbol lead no. i/o/p type name/function - 38 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 mpa16 mpa15 mpa14 mpa13 mpa12 mpa11 mpa10 mpa09 mpa08 mpa07 mpa06 mpa05 mpa04 mpa03 mpa02 mpa01 mpa00 af18 ad17 ae17 ab16 af17 ac16 ad16 ae16 af16 ab15 ac15 ad15 ae15 af15 ac14 ad14 ae14 ilvttl address bus: these leads are the address bus used by the host processor for accessing the ethermap-12 for a read or write cycle. mpa16 is the most significant bit in the location ? s address. motorola notation: a[ ] mpd15 mpd14 mpd13 mpd12 mpd11 mpd10 mpd09 mpd08 mpd07 mpd06 mpd05 mpd04 mpd03 mpd02 mpd01 mpd00 ac20 af22 ab19 ae21 ad20 af21 ac19 ae20 ab18 ad19 af20 ac18 ae19 af19 ad18 ab17 i/o(t) lvttl/ lv c m o s 8ma data bus: these leads are the bidirectional data bus used for transferring data between the ethermap-12 and the host proc- essor. mpd15 is the most significant bit. motorola notation: d[ ] mpsel ad21 i lvttl ethermap-12 chip select (active low): this active low lead enables data transfers between the host processor and the ethermap-12 through a read or write cycle. motorola notation: cs mpts ae22 i lvttl data strobe (active low): this active low lead initiates a (read or write) transfer between the host processor and the ether- map-12. motorola notation: ds mpwr af23 i lvttl read/write (active low): this active low lead indicates that the actual transfer between the host processor and the ether- map-12 is a write transfer. motorola notation: r/w symbol lead no. i/o/p type name/function - 39 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 motorola mpc860 - host processor interface mpack ab20 o(t) lvcmos 24ma data transfer acknowledge (active low): for a write access, an active edge on this lead indicates that data is written to the addressed memory location. for a read access, an active edge on this lead indicates that the data to be read from the addressed memory location is available on the data bus. motorola notation: dsack mpintr ac21 o lvcmos 8ma interrupt request (active low): this lead signals an interrupt request to the host processor. symbol lead no. i/o/p type name/function mpclk ad23 i lvttl microprocessor clock: this lead is the clock sourced by the microprocessor being interfaced to this device. its max. frequency is 50 mhz. motorola mpc860 notation: clk mpa16 mpa15 mpa14 mpa13 mpa12 mpa11 mpa10 mpa09 mpa08 mpa07 mpa06 mpa05 mpa04 mpa03 mpa02 mpa01 mpa00 af18 ad17 ae17 ab16 af17 ac16 ad16 ae16 af16 ab15 ac15 ad15 ae15 af15 ac14 ad14 ae14 ilvttl address bus: these leads are the address bus used by the host processor for accessing the ethermap-12 for a read or write cycle. mpa16 is the most significant bit in the location ? s address. motorola mpc860 notation: a[ ] symbol lead no. i/o/p type name/function - 40 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 mpd15 mpd14 mpd13 mpd12 mpd11 mpd10 mpd09 mpd08 mpd07 mpd06 mpd05 mpd04 mpd03 mpd02 mpd01 mpd00 ac20 af22 ab19 ae21 ad20 af21 ac19 ae20 ab18 ad19 af20 ac18 ae19 af19 ad18 ab17 i/o(t) lvttl/ lv c m o s 8ma data bus: these leads are the bidirectional data bus used for transferring data between the ethermap-12 and the host proc- essor. mpd15 is the most significant bit. motorola mpc860 notation: d[ ] mpsel ad21 i lvttl ethermap-12 chip select (active low): this active low lead enables data transfers between the host processor and the ethermap-12 through a read or write cycle. motorola mpc860 notation: cs mpts ae22 i lvttl transfer start (active low): this active low lead initiates a (read or write) transfer between the host processor and the ethermap-12. it is active low only during the first cycle of the access. motorola mpc860 notation: ts mpwr af23 i lvttl read/write (active low): this active low lead indicates that the actual transfer between the host processor and the ether- map-12 is a write transfer. motorola mpc860 notation: rd/wr mpack ab20 o(t) lvcmos 24ma transfer acknowledge (active low): this active low lead is used to acknowledge a host processor access. it is synchro- nous to the mpclk. to acknowledge an access, mpack is asserted during 1 mpclk cycle. for a write access, an acknowledge indicates that data is writ- ten to the addressed memory location. for a read access, an acknowledge indicates that the data to be read from the addressed memory location is available on the data bus. motorola mpc860 notation: ta mpintr ac21 o lvcmos 8ma interrupt request (active low): this lead signals an interrupt request to the host processor. symbol lead no. i/o/p type name/function - 41 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 motorola mpc8260 local bus - host processor interface symbol lead no. i/o/p type name/function mpclk ad23 i lvttl microprocessor clock: this lead is the clock sourced by the microprocessor being interfaced to this device. its max. frequency is 50 mhz. motorola mpc8260 notation: clk mpa16 mpa15 mpa14 mpa13 mpa12 mpa11 mpa10 mpa09 mpa08 mpa07 mpa06 mpa05 mpa04 mpa03 mpa02 mpa01 mpa00 af18 ad17 ae17 ab16 af17 ac16 ad16 ae16 af16 ab15 ac15 ad15 ae15 af15 ac14 ad14 ae14 ilvttl local address bus: these leads are the address bus used by the host processor for accessing the ethermap-12 for a read or write cycle. mpa16 is the most significant bit in the location ? s address. motorola mpc8260 notation: l_a[ ] mpd15 mpd14 mpd13 mpd12 mpd11 mpd10 mpd09 mpd08 mpd07 mpd06 mpd05 mpd04 mpd03 mpd02 mpd01 mpd00 ac20 af22 ab19 ae21 ad20 af21 ac19 ae20 ab18 ad19 af20 ac18 ae19 af19 ad18 ab17 i/o(t) lvttl/ lv c m o s 8ma local data bus: these leads are the bidirectional data bus used for transferring data between the ethermap-12 and the host processor. mpd15 is the most significant bit. motorola mpc8260 notation: lcl_d[ ] mpsel ad21 i lvttl ethermap-12 chip select (active low): this active low lead enables data transfers between the host processor and the ethermap-12 through a read or write cycle. motorola mpc8260 notation: cs mpts ae22 i lvttl not applicable input: this lead must be tied to vss. - 42 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 boundary scan (ieee standard 1149.1) mpwr af23 i lvttl local bus read/write (active low): this active low lead indi- cates that the actual transfer between the host processor and the ethermap-12 is a write transfer. motorola mpc8260 notation: lwr mpack ab20 o(t) lvcmos 24ma local bus gpcm transfer acknowledge (active low): this lead is used to acknowledge a host processor access. it is syn- chronous to the mpclk. to acknowledge an access, mpack is asserted during 1 mpclk cycle and then de-asserted during 3 mpclk cycles before going in tristate. for a write access, an acknowledge indicates that data is writ- ten to the addressed memory location. for a read access, an acknowledge indicates that the data to be read from the addressed memory location is available on the data bus. motorola mpc8260 notation: lgta mpintr ac21 o lvcmos 8ma interrupt request (active low): this lead signals an interrupt request to the host processor. symbol lead no. i/o/p type name/function tck f2 i lvttl-5 test boundary scan clock: this signal is used to shift data into tdi on its rising edge and out of tdo on its falling edge. the maximum clock frequency is 10 mhz. tdi d1 i lvttl-5p test boundary scan data input: serial test instructions and data are clocked into this lead on the rising edge of tck. this lead has an internal pull-up resistor. tdo e2 o lvcmos 8 ma test boundary scan data output: serial data test instructions and data are clocked out of this lead on the falling edge of tck. when inactive, this lead goes to a high impedance state. tms f3 i lvttl-5p test boundary scan mode select: this input lead is sampled on the rising edge of tck. it is used to place the test access port controller into various states, as defined in ieee 1149.1. an internal pull-up holds this lead high during normal operation. this lead has an internal pull-up resistor. trst e1 i lvttl-5p test boundary scan reset: an active low signal that asynchronously resets the test access port controller. the reset must be present for a minimum of 250 ns. this lead has an internal pull-up resistor. symbol lead no. i/o/p type name/function - 43 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 test symbol lead no. i/o/p type name/function scanen ab25 i lvttl-5d scan enable: this lead is used for transwitch testing pur- poses only. this lead has an internal pull-down to vss and should be held low. scanmode af5 i lvttl-5d scan mode: this lead is used for transwitch testing pur- poses only. this lead has an internal pull-down to vss and should be held low. testin8 ae5 i lvttl-5d test input: this lead is used for transwitch testing purposes only. this lead has an internal pull-down to vss and should be held low. pllbypass aa24 i lvttl-5d pll bypass: this lead is used for transwitch testing pur- poses only. this lead should be held low for correct operation. pllbypass has an internal pull-down to vss. pllout y23 o lvcmos 4ma pll output: this lead is used for transwitch testing pur- poses only. this lead should be left open (floating). mbistmode ac26 i lvttl-5d memory bist: this lead is used for transwitch testing pur- poses only. this lead has an internal pull-down to vss and should be held low. testin7 testin6 testin5 testin4 testin3 testin2 testin1 testin0 h2 g1 g2 h4 h3 g3 f1 h5 i lvttl-5p test input: these leads are used for transwitch testing pur- poses only. these leads have internal pull-ups to vdd and should be held high. testout7 testout6 testout5 testout4 testout3 testout2 testout1 testout0 ab7 ac6 ad5 ae4 ad4 h1 j2 j4 olvcmos 4ma test output: these leads are used for transwitch testing purposes only. these leads should be left open (floating). - 44 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 scanin39 scanin38 scanin37 scanin36 scanin35 scanin34 scanin33 scanin32 scanin31 scanin30 scanin29 scanin28 scanin27 scanin26 scanin25 scanin24 scanin23 scanin22 scanin21 scanin20 scanin19 scanin18 scanin17 scanin16 scanin15 scanin14 scanin13 scanin12 scanin11 scanin10 scanin9 scanin8 g24 f25 h22 e26 g23 f24 e25 d26 g22 f23 e24 d25 d24 f22 c23 b23 c22 d21 e20 a23 b22 c21 d20 c5 b4 c4 d5 e4 d3 d2 e3 f4 ilvttl-5 test input: these leads are used for transwitch testing pur- poses only. these leads should be held low. symbol lead no. i/o/p type name/function - 45 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 absolute maximum ratings and environmental limitations ( referenced to vss ) notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the ? caution ? label on the drypack bag in which devices are supplied. 3. test method for esd per mil-std-883e, method 3015.7. 4. device core is 1.2 v only. all input signals leads accept 5v signals except for smii/gmii and sdram memory interface signals which accept only 3.3v signals. thermal characteristics power requirements note: 1. this is an approximate value. parameter symbol min max unit conditions i/o supply voltage (3.3v) v dd33 -0.3 3.9 v note 1, 4 core supply voltage (1.2v) v dd12 -0.3 1.4 v note 1, 4 dc input voltage lvttl input voltage lvttl-5 input voltage v in 0 -0.5 3.3 5.5 v note 1, 4 storage temperature range t s -55 +150 o c note 1 ambient operating temperature t a -40 +85 o c 0 ft/min linear airflow moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd 2 kv note 3 parameter min typ max unit test conditions thermal resistance: junction to ambient 16 o c/w test performed with package assem- bled on jedec standard multi-layer test board with 0 ft/min linear airflow. parameter min typ max unit test conditions v dd33 3.135 3.30 3.465 v i dd33 tbd ma v dd12 1.14 1.20 1.26 v i dd12 tbd ma power dissipation, p ddtotal tbd w - 46 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 input, output and input/output parameters input parameters for lvttl-5 (5 volt tolerant) input parameters for lvttl-5p (5 volt tolerant, with pull-up resistor) input parameters for lvttl-5d (5 volt tolerant, with pull-down resistor) input parameters for lvttl (3.3 volt tolerant) parameter min typ max unit test conditions v ih 2.0 5.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a av dd33 = 3.45, vin = v dd or gnd input capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 5.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 100 av dd33 =3.45; input = 0 volts input capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 5.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current -100 av dd33 = 3.45; input = 3.45 volts input capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 av dd33 = 3.45, vin = v dd or gnd input capacitance 5 pf - 47 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 output parameters for lvcmos 24ma (open drain) note: open drain requires use of a 4.7 k ? external pull-up resistor to v dd33 . output parameters for lvcmos 12ma output parameters for lvcmos 8ma parameter min typ max unit test conditions output capacitance tbd pf v oh 2.4 v v dd33 = 3.15; i oh = -24.0 v ol 0.4 v v dd33 = 3.15; i ol = 24.0 i ol 24 ma i oh -24 ma t rise 1.23 2.74 ns c load = 30 pf t fall 1.07 2.72 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input parameter min typ max unit test conditions output capacitance tbd pf v oh 2.4 v v dd33 = 3.15; i oh = -12.0 v ol 0.4 v v dd33 = 3.15; i ol = 12.0 i ol 12 ma i oh -12 ma t rise 1.58 3.38 ns c load = 30 pf t fall 1.38 3.47 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input parameter min typ max unit test conditions output capacitance tbd pf v oh 2.4 v v dd33 = 3.15; i oh = -8.0 v ol 0.4 v v dd33 = 3.15; i ol = 8.0 i ol 8ma i oh -8 ma t rise 1.87 3.90 ns c load = 30 pf t fall 1.80 4.42 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input - 48 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 output parameters for lvcmos 4ma input/output parameters for lvttl-5 input and lvcmos output 12ma (5 volt tolerant input) input/output parameters for lvttl-5 input and lvcmos output 8ma (5 volt tolerant input) parameter min typ max unit test conditions v oh 2.4 v v dd33 = 3.15; i oh = -4.0 v ol 0.4 v v dd33 = 3.15; i ol = 4.0 i ol 4ma i oh -4 ma t rise 2.81 6.02 ns c load = 30 pf t fall 3.15 7.34 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input output capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a 0 to 3.3 v input input capacitance 5 pf v oh 2.4 v v dd33 = 3.15; i oh = -12.0 v ol 0.4 v v dd33 = 3.15; i ol = 12.0 i ol 12 ma i oh -12 ma t rise 1.58 3.38 ns c load = 30 pf t fall 1.38 3.47 ns c load = 30 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a 0 to 3.3 v input input capacitance 5 pf v oh 2.4 v v dd33 = 3.15; i oh = -8.0 v ol 0.4 v v dd33 = 3.15; i ol = 8.0 i ol 8ma i oh -8 ma t rise 1.87 3.91 ns c load = 30 pf t fall 1.80 4.43 ns c load = 30 pf - 49 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 input/output parameters for lvttl input and lv3cmos output 16ma (5v volt tolerant input) parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a 0 to 3.3 v input input capacitance 5 pf v oh 2.4 v v dd33 = 3.15; i oh = -16.0 v ol 0.4 v v dd33 = 3.15; i ol = 16.0 i ol 16 ma i oh -16 ma t rise 1.32 2.90 ns c load = 30 pf t fall 1.19 3.07 ns c load = 30 pf - 50 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 timing characteristics this section presents the detailed timing characteristics for the ethermap-12 in figures 7 through 35 with val- ues of the timing parameters tabulated below each waveform diagram. all outputs are measured with a maxi- mum load capacitance of 50 pf unless otherwise stated. timing parameters are measured at the voltage levels of (v oh +v ol )/2 for output signals and (v ih + v il )/2 for input signals. figure 7. drop bus timing 50 pf load notes: 1. the optional v1 pulse only occurs during the first frame of the low order multi-frame as indicated by the h4 byte. it is always located twelve clock cycles after the corresponding j1 pulse. 2. the active tbdclk clock edge on which the data/parity and timing signals are clocked out can be selected, see ? drop bus interface ? on page 176 . the waveforms shown correspond to the negative clock edge selection. 3. an additional delay of 0 up to 15 extra tbdclk clock cycles can be inserted between the drop bus timing and the drop bus data/parity signals, tbdc1j1v1 and tbdspe, see ? drop bus interface ? on page 176 . the wave- forms shown correspond to a delay of 0 clock cycles. parameter symbol min typ max unit tbdclk clock period t cyc 12.86 ns tbdclk duty cycle t pwh 40 50 60 %t cyc tbdc1j1v1/tbdspe/tbdd(7-0)/tbdpar setup time to tbdclk t s 3ns tbdc1j1v1/tbdspe/tbdd(7-0)/tbdpar hold time after tbdclk t h 0ns tbdd(7-0)/tbdpar (input) tbdspe (input) tbdc1j1v1 (input) tbdclk (input) t cyc t pwh t s t h c1/j0 pulse j1 pulse #1 j1 pulse #2 j1 pulse #12 v1 pulse #1 v1 pulse #2 j1 #1 - 51 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 8. add bus timing (timing signals are inputs) 50 pf load notes: 1. the optional v1 pulse only occurs during the first frame of the low order multi-frame as indicated by the h4 byte. it is always located twelve clock cycles after the corresponding j1 pulse. 2. the active rtclk clock edge on which the data/parity signals are clocked out can be selected, see ? add bus interface ? on page 177 . the waveforms shown correspond to the positive clock edge selection. 3. the active rtclk clock edge on which the timing signals are sampled can be selected, see ? add bus interface ? on page 177 . the waveforms shown correspond to the negative clock edge selection. 4. an additional delay of 0 up to 15 extra rtclk clock cycles can be inserted between the add bus timing and the add bus data/parity signals, tbac1j1v1 and tbaspe, see ? add bus interface ? on page 177 . the waveforms shown correspond to a delay of 0 clock cycles. parameter symbol min typ max unit rtclk clock period t cyc 12.86 ns rtclk duty cycle t pwh 40 50 60 %t cyc tbac1j1v1/aspe setup time before rtclk t s 3ns tbac1j1v1/aspe hold time after rtclk t h 0ns tba dd add indicator delayed from rtcl t d(1) 16ns tbad(7-0)/apar out valid delay from rtclk t d(2) 16ns tbad(7-0)/apar to tristate delay from rtclk t d(3) 16ns tbad(7-0)/apar out tristate to driven delay from rtclk t d(4) 16ns tbad(7-0)/tbapar (output) tbaspe (input) tbac1j1v1 (input) rtclk (input) t cyc t pwh t s t h c1/j0 pulse j1 pulse #1 j1 pulse #2 j1 pulse #12 v1 pulse #1 v1 pulse #2 tba dd (output) t d(1) t d(2) t d(4) t d(3) - 52 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 9. add bus timing (timing signals are outputs) 50 pf load parameter symbol min typ max unit rtclk clock period t cyc 12.86 ns rtclk duty cycle t pwh 40 50 60 %t cyc rtfs/rtmfs setup time to rtclk t s 3ns rtfs/rtmfs hold time after rtclk t h 0ns tbadd add indicator delayed from rtclk t d(1) 16ns tbad(7-0)/tbapar out valid delay from rtclk t d(2) 16ns tbad(7-0)/tbapar to tristate delay from rtclk t d(3) 16ns tbad(7-0)/tbapar out tristate to driven delay from rtclk t d(4) 16ns tbac1j1v/tbaspe out valid delay from rtclk t d(5) 16ns bad(7-0)/tbapar (output) tbaspe (output) tbac1j1v1 (output) c1/j0 pulse j1 pulse #1 j1 pulse #2 j1 pulse #12 v1 pulse #1 tb add (output) t d(1) t d(2) t d(4) t d(3) rtfs (input) rtclk (input) t cyc t pwh rtmfs (input) t s t h (pulse every 4 frames) t d(5) v1 pulse #2 - 53 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 notes: 1. the optional v1 pulse only occurs during the first frame of the low order multi-frame as indicated by the h4 byte. it is always located twelve clock cycles after the corresponding j1 pulse. 2. the active rtclk clock edge on which the data/parity and timing signals are clocked out can be selected, see ? add bus interface ? on page 177 . the waveforms shown correspond to the positive clock edge selection. 3. the active rtclk clock edge on which the rtfs/rtmfs signals are sampled can be selected, see ? add bus interface ? on page 177 . the waveforms shown correspond to the positive clock edge selection. 4. an additional delay of 0 up to 15 extra rtclk clock cycles can be inserted between the add bus timing and the add bus data/parity signals, tbac1j1v1 and tbaspe, see ? add bus interface ? on page 177 . the waveforms shown correspond to a delay of 0 clock cycles. figure 10. tx gmii ethernet interface 5 pf load parameter symbol min typ max unit etntxgclk clock period t cyc 8ns etntxgclk duty cycle, t pwh /t cyc t pwh 40 60 ns etntxen out valid delay from etntxgclk t d(1) 1.5 4.5 ns etntxd(7-0) out valid delay from etntxgclk t d(2) 1.5 4.5 ns etntxer out valid delay from etntxgclk t d(3) 1.5 4.5 ns (output) etntxd(7-0) (output) etntxen (output) etntxgclk (output) t cyc etntxer t pwh t d(1) t d(3) t d(2) - 54 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 11. rx gmii ethernet interface 10 pf load parameter symbol min typ max unit etnrxclk clock period t cyc 8ns etnrxclk duty cycle, t pwh /t cyc t pwh 45 55 % etnrxdv setup time before etnrxclk t s(1) 2ns etnrxdv hold time after etnrxclk t h(1) 0ns etnrxd(7-0) setup time before etnrxclk t s(2) 2ns etnrxd(7-0) hold time after etnrxclk t h(2) 0ns etnrxer setup time before etnrxclk t s(3) 2ns etnrxer hold time after etnrxclk t h(3) 0ns (input) etnrxd(7-0) (input) etnrxdv (input) etnrxclk (input) t cyc etnrxer t pwh t h(1) t s(2) t s(1) t h(2) t s(3) t h(3) - 55 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 12. tx/rx smii ethernet interface (with sync as output) 10 pf load parameter symbol min typ max unit etnrxclk clock period t cyc 8ns etnrxclk duty cycle, t pwh /t cyc t pwh 40 60 % etntxen out valid delay from etnrxclk t d(1) 1.5 4.5 ns etntxdn out valid delay from etnrxclk t d(2) 1.5 4.5 ns etnrxdn setup time before etnrxclk t s 1.5 ns etnrxdn hold time after etnrxclk t h 1ns (input) etntxdn (output) etntxen (output) etnrxclk (input) t cyc etnrxdn t pwh t s t d(2) t d(1) tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 tx_er txd0 tx_en txd1 txd2 txd7 txd6 crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs rxd0 rx_dv rxd1 rxd2 rxd7 rxd6 t h n = 1 - 8 - 56 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 13. tx/rx smii ethernet interface (with sync as input) 10 pf load parameter symbol min typ max unit etnrxclk clock period t cyc 8ns etnrxclk duty cycle, t pwh /t cyc 40 60 % etntxen setup time before etnrxclk t s1 1.5 ns etntxen hold time after etnrxclk t h1 1 etntxdn out valid delay from etnrxclk t d(2) 1.5 4.5 ns etnrxdn setup time before etnrxclk t s 1.5 ns etnrxdn hold time after etnrxclk t h 1ns (input) etntxdn (output) etntxen (input) etnrxclk (input) t cyc etnrxdn t pwh t s t d(2) tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 tx_er txd0 tx_en txd1 txd2 txd7 txd6 crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs rxd0 rx_dv rxd1 rxd2 rxd7 rxd6 t h n = 1 - 8 t s1 t h1 - 57 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 14. ethernet management interface 10 pf load parameter symbol min typ max unit etnmdc clock period t cyc tbd ns etnmdc duty cycle, t pwh /t cyc t pwh tbd tbd ns etnmdio out valid delay from etnmdc t d 15 30 ns etnmdio setup time before etnmdc t s 5ns etnmdio hold time after etnmdc t h 5ns etnmdio (output) etnmdc (output) t cyc t pwh t d t h etnmdio (input) t s read operation write operation - 58 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 15. sdram interface - single word read 30 pf load note: # means 1 or 2 depending on the number of the sdram. parameter symbol min typ max unit sd#clka/b clock period t cyc 8ns sd#clka/b duty cycle, t pwh /t cyc t pwh 45 55 % sd#clke valid delay from sd#clk t d(1) 25ns sd#cs valid delay from sd#clk t d(2) 25ns sd#ras valid delay from sd#clk t d(3) 25ns sd#cas valid delay from sd#clk t d(4) 25ns sd#we valid delay from sd#clk t d(5) 25ns sd#ba(1-0) valid delay from sd#clk t d(7) 25ns sd#a(12-0) valid delay from sd#clk t d(8) 25ns sd#d(31-0) setup time to sd#clkb t s 1ns sd#d(31-0) hold time from sd#clkb t h 1ns active read read nop active active active read nop read f 0 2 0 1 3 2 d0 d1 d3 d2 d4 3 d5 d6 d7 sd#clka/b sd# ras sd# cas sd# mask sd# ba(1-0) sd# a(12-0) sd# d(31-0) sd#clke sd# cs1 1 sd# we cas latency = 3 t cyc t pwh t d(1) t d(2) t d(4) t d(3) t d(5) t d(7) t d(8) t s t h sd#cs2 - 59 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 16. sdram interface - single word write 30 pf load note:1 for burst accesses t d(10) and t d(11) apply as the delay parameters between successive data bytes. parameter symbol min typ max unit sd#clka clock period t cyc 8ns sd#clka duty cycle, t pwh /t cyc t pwh 45 55 % sd#clke valid delay from sd#clka t d(1) 25ns sd#cs valid delay from sd#clka t d(2) 25ns sd#ras valid delay from sd#clka t d(3) 25ns sd#cas valid delay from sd#clka t d(4) 25ns sd#we valid delay from sd#clka t d(5) 25ns sd#mask valid delay from sd#clka t d(6) 25ns sd#ba(1-0) valid delay from sd#clka t d(7) 25ns sd#a(12-0) valid delay from sd#clka t d(8) 25ns sd#d(31-0) tristate to driven from sd#clka t d(9) 25ns sd#d(31-0) valid delay from sd#clka t d(10) 25ns sd#d(31-0) valid hold from sd#clka t d(11) 25ns sd#d(31-0) driven to tristate from sd#clka t d(12) 25ns active write write nop active active active write nop write f 0 2 0 1 3 2 d0 d1 d3 d2 d4 3 d5 d6 d7 sd#clka sd#ras sd#mask sd# ba(1-0) sd# a(12-0) sd# d(31-0) sd#clke sd# cs 1 1 sd#we sd#cas t cyc t pwh t d(1) t d(2) t d(3) t d(4) t d(5) t d(7) t d(8) t d(9) t d(10) t d(11) t d(12) sd#cs2 - 60 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 17. sdram interface - burst read 30 pf load parameter symbol min typ max unit sd#clka/b clock period t cyc 8ns sd#clka/b duty cycle, t pwh /t cyc 45 55 % sd#clke valid delay from sd#clka t d(1) 25ns sd# cs valid delay from sd#clka t d(2) 25ns sd# ras valid delay from sd#clka t d(3) 25ns sd# cas valid delay from sd#clk t d(4) 25ns sd# we valid delay from sd#clka t d(5) 25ns sd# ba(1-0) valid delay from sd#clka t d(7) 25ns sd# a(12-0) valid delay from sd#clka t d(8) 25ns sd# d(31-0) setup time to sd#clkb t s 1ns sd# d(31-0) hold time from sd#clkb t h 1ns active read* read* nop active active active read* nop read* 1 0 2 3 1 * * * d0 d1 d3 d2 d4 3 d5 d6 d7 sd#clka/b sd# ras sd# cas sd#mask sd#bk(1-0) sd#a(12-0) sd#d(31-0) sd#cke sd# cs 1 2 sd# we cas latency = 3 t s t h * note*: all read commands enable the auto precharge feature with addr(10)=1 0 t cyc t pwh t d(1) t d(2) t d(3) t d(4) t d(5) t d(7) t d(8) sd#cs2 # means sdram 1 or sdram 2 - 61 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 18. sdram interface - burst write 30 pf load note: for burst accesses t d(10) and t h apply as the delay and hold parameters between successive data bytes. parameter symbol min typ max unit sd#clka clock period t cyc 8ns sd#clka duty cycle, t pwh /t cyc 45 55 % sd#clke valid delay from sd#clka t d(1) 25ns sd#cs valid delay from sd#clka t d(2) 25ns sd#ras valid delay from sd#clka t d(3) 25ns sd#cas valid delay from sd#clka t d(4) 25ns sd#we valid delay from sd#clka t d(5) 25ns sd#ba(1-0) valid delay from sd#clka t d(7) 25ns sd#a(12-0) valid delay from sd#clka t d(8) 25ns sd#d(31-0) tristate to driven from sd#clka t d(9) 25ns sd#d(31-0) valid delay from sd#clka t d(10) 25ns sd#d(31-0) valid hold from sd#clk t h 25ns sd#d(31-0) driven to tristate from sd#clka t d(12) 25ns active write* nop active active active nop 1 0 2 3 1 * * * d0 d1 d3 d2 d4 3 d5 d6 d7 sd#clka sd#ras sd#mask sd#bk(1-0) sd#a(12-0) sd#d(31-0) sd#cke sd#cs 2 sd#we sd#cas write* write* write* * note*: all write commands enable the auto precharge feature with addr(10)=1 0 t cyc t pwh t d(1) t d(2) t d(3) t d(4) t d(5) t d(7) t d(8) t d(9) t d(10) t h t d(12) # means sdram1 and sdram2 - 62 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 19. rx high order poh byte interface 50 pf load parameter symbol min typ max unit pohrxclk clock period t cyc 12.86 ns pohrxclk clock pulse width t pwh 40 50 60 %t cyc pohrxale/pohrxadd out valid delay from pohrxclk t d(1) 14ns pohrxdle/pohrxdat out valid delay from pohrxclk t d(2) 14ns pohrxdat (output) (output) pohrxadd (output) pohrxale (output) pohrxclk (output) pohrxdle poh data address a0 a6 a7 d0 d6 d7 t d(1) t d(2) t cyc t pwh - 63 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 20. tx high order poh byte interface 50 pf load parameter symbol min typ max unit pohtxclk clock period t cyc 12.86 ns pohtxclk clock pulse width 40 50 60 %t cyc pohtxale/pohtxadd out valid delay from pohtxclk t d(1) 14ns pohtxdle out valid delay from pohtxclk t d(2) 14ns pohtxdat setup time before pohtxclk t s 3ns pohtxdat hold time after pohtxclk t h 0ns pohrxdat (input) (output) pohrxadd (output) pohrxale (output) pohrxclk (output) pohrxdle address a0 a6 a7 d0 d6 d7 t d(1) t d(2) t cyc t pwh t s t h - 64 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 21. rx low order poh byte interface 50 pf load parameter symbol min typ max unit pohrxclk1 clock period t cyc 12.86 ns pohrxclk1 clock pulse width t pwh 40 50 60 %t cyc pohrxale1/pohrxadd1 out valid delay from pohrxclk1 t d(1) 14ns pohrxdle1/pohrxdat1 out valid delay from pohrxclk1 t d(2) 14ns pohrxdat1 (output) (output) pohrxadd1 (output) pohrxale1 (output) pohrxclk1 (output) pohrxdle1 poh data address a0 a10 a11 d0 d6 d7 t d(1) t d(2) t cyc t pwh - 65 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 22. tx low order poh byte interface 50 pf load parameter symbol min typ max unit pohtxclk1 clock period t cyc 12.86 ns pohtxclk1 clock pulse width 40 50 60 %t cyc pohtxale1/pohtxadd1 out valid delay from pohtxclk1 t d(1) 14ns pohtxdle1 out valid delay from pohtxclk 1 t d(2) 14ns pohtxdat1 setup time before pohtxclk1 t s 3ns pohtxdat1 hold time after pohtxclk1 t h 0ns pohtxdat1 (input) (output) pohtxadd1 (output) pohtxale1 (output) pohtxclk1 (output) pohtxdle1 address a0 a10 a11 d0 d6 d7 t d(1) t d(2) t cyc t pwh t s t h - 66 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 23. rx high order alarm indication port interface 50 pf load notes: 1. all the output signals are synchronous of the rising edge of internal clock sysclk(rtclk=77.76mhz). 2. the minimum value of t d (1 ns) is maintained because the data and framing pulse are placed on the output when the rising edge of the ringrxipc is placed on the output. the maximum value of t d is maintained also. parameter symbol min typ max unit ringrxipc clock period t cyc 51.44 ns ringrxipc clock pulse width t pwh 40 50 60 %t cyc ringrxipf/ringrxipd out valid delay from ringrxipc t d 16ns ringrxipf (output) ringrxipc (output) bit #1 t d t cyc t pwh ringrxipd (output) bit #2 bit #3 last bit .... - 67 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 24. tx high order alarm indication port interface 50 pf load parameter symbol min typ max unit ringtxipc clock period t cyc 51.44 ns ringtxipc clock pulse width t pwh 40 50 60 %t cyc ringtxipf/ringtxipd setup time before ringtxipc t s 30 ns ringtxipf/ringtxipd hold time after ringtxipc t h 0ns ringtxipf (input) ringtxipc (input) bit #1 t s t cyc t pwh ringtxipd (input) bit #2 bit #3 last bit .... t h - 68 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 25. rx low order alarm indication port interface 50 pf load notes: 1. all the output signals are synchronous of the rising edge of internal clock sysclk(rtclk=77.76mhz). 2. the minimum value of t d (1 ns) is maintained because the data and framing pulse are placed on the output when the rising edge of the ringrxipc1 is placed on the output. the maximum value of t d is maintained also. parameter symbol min typ max unit ringrxipc1 clock period t cyc 51.44 ns ringrxipc1 clock pulse width t pwh 40 50 60 %t cyc ringrxipf/ringrxipd out valid delay from ringrxipc1 t d 16ns ringrxipf1 (output) ringrxipc1 (output) bit #1 t d t cyc t pwh ringrxipd1 (output) bit #2 bit #3 last bit .... - 69 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 26. tx low order alarm indication port interface 50 pf load parameter symbol min typ max unit ringtxipc1 clock period t cyc 51.44 ns ringtxipc1 clock pulse width t pwh 40 50 60 %t cyc ringtxipf1/ringtxipd1 setup time before ringtxipc1 t s 30 ns ringtxipf1/ringtxipd1 hold time after ringtxipc1 t h 0ns ringtxipf1 (input) ringtxipc1 (input) bit #1 t s t cyc t pwh ringtxipd1 (input) bit #2 bit #3 last bit .... t h - 70 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 27. microprocessor interface: generic intel mode write cycle 1 1. see the lead description table on generic intel - host processor interface for the mapping to i/o leads. a rd cs d rdy t su(1) t d(5) t su(2) t h(1) t h(4) clk wr t su(4) t d(2) t d(7) t d(6) t cyc t l t h t su(3) t h(3) t h(2) t d(1) t d(3) t d(4) t d(10) - 71 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - a setup time before wr t su(1) -0.9*t cyc - rd setup time before wr t su(2) a a. only applies if a write access is preceded by a read access. 0-ns cs setup time before wr t su(3) b b. cs may stay low between 2 successive accesses to the same peripheral. 0-ns d setup time before wr t su(4) -0.9*t cyc - hold time of a to active edge rdy t h(1) 0-ns rd hold time after wr t h2 c c. only applies if a write access is followed by a read access. t cyc - cs hold time after wr t h(3) b, d d. no timing constraint between the rising edges of cs and wr are defined. cs is only latched at the beginning of an access. -- hold time of d to active edge rdy t h(4) 0-ns delay from wr to rdy driving t d(1) 020ns delay from clk to active edge rdy t d(2) 08ns delay from wr to inactive edge rdy t d(3) 07ns delay from rdy going inactive to rdy going in tristate t d(4) 5-ns delay from wr to rdy going in tristate t d(5) -20ns wr inactive pulse width t d(6) t cyc - response latency t d(7) tbd tbd cs inactive pulse width t d(10) e e. between accesses to different peripherals. t cyc - - 72 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 28. microprocessor interface: generic intel mode read cycle 1 1. see the lead description table on generic intel - host processor interface for the mapping to i/o leads. a wr cs d rdy t su(1) t d(5) t su(2) t h(1) t d(9) clk rd t d(2) t d(7) t d(6) t cyc t l t h t su(3) t h(3) t h(2) t d(1) t d(8) t d(3) t d(4) t su(4) t d(10) - 73 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - a setup time before rd t su(1) -0.9*t cyc - wr setup time before rd t su(2) a a. only applies if a read access is preceded by a write access. 0-ns cs setup time before rd t su(3) b b. cs may stay low between 2 successive accesses to the same peripheral. 0-ns d setup time before rdy t su(4) 0.7*t cyc - a hold time after active edge rdy t h(1) 0-ns wr hold time after rd t h(2) c c. only applies if a read access is followed by a write access. t cyc - cs hold time after rd t h(3) b, d d. no timing constraint between the rising edges of cs and rd are defined. cs is only latched at the beginning of an access. -- delay from rd to rdy driving t d(1) 020ns delay from clk to active edge rdy t d(2) 08ns delay from rd to inactive edge rdy t d(3) 07ns delay from rdy going inactive to rdy going in tristate t d(4) 5-ns delay from rd to rdy going in tristate t d(5) -20ns rd inactive pulse width t d(6) t cyc - response latency t d(7) tbd tbd delay from rd to d driving t d(8) 012ns delay from rd to d going in tristate t d(9) 012ns cs inactive pulse width t d(10) e e. between accesses to different peripherals t cyc - - 74 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 29. microprocessor interface: generic motorola mode write cycle 1 1. see the lead description table on generic motorola - host processor interface for the mapping to i/o leads. a r/w cs d dsack t su(1) t d(5) t su(2) t h(1) t h(4) clk ds t su(4) t d(2) t d(7) t d(6) t cyc t l t h t su(3) t h(3) t h(2) t d(1) t d(3) t d(4) t d(10) - 75 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - a setup time before ds t su(1) -0.9*t cyc - r/w setup time before ds t su(2) a a. only applies if a write access is preceded by a read access. r/w may stay low between 2 successive write accesses. 0-ns cs setup time before ds t su(3) b b. cs may stay low between 2 successive accesses to the same peripheral. 0-ns d setup time before ds t su(4) -0.9*t cyc - a hold time after dsack t h(1) 0-ns r/w hold time after ds t h(2) c c. only applies if a write access is followed by a read access. r/w may stay low between 2 successive write accesses. 0-ns cs hold time after ds t h(3) b, d d. no timing constraint between the rising edges of cs and ds are defined, since no such relationship is defined in the mc68360 data sheet. cs is only latched at the beginning of an access. -- d hold time after active edge dsack t h(4) 0-ns delay from ds to dsack driving t d(1) 020ns delay from clk to active edge dsack t d(2) 08ns delay from ds to inactive edge dsack t d(3) 07ns delay from dsack going inactive to dsack going in tristate t d(4) 5-ns delay from ds to dsack going in tristate t d(5) -20ns ds inactive pulse width t d(6) t cyc - response latency t d(7) tbd tbd cs inactive pulse width t d(10) e e. between accesses to different peripherals t cyc - - 76 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 30. microprocessor interface: generic motorola mode read cycle 1 1. see the lead description table on generic motorola - host processor interface for the mapping to i/o leads. a r/w cs d dsack t su(1) t d(5) t su(2) t h(1) t d(9) clk ds t d(2) t d(7) t d(6) t cyc t l t h t su(3) t h(3) t h(2) t d(1) t d(8) t d(3) t d(4) t su(4) t d(10) - 77 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - a setup time before ds t su(1) -0.9*t cyc - r/w setup time before ds t su(2) a a. only applies if a read access is preceded by a write access. r/w may stay high between 2 successive read accesses. 0-ns cs setup time before ds t su(3) b b. cs may stay low between 2 successive accesses to the same peripheral. 0-ns d setup time to active edge dsack t su(4) 0.7*t cyc - a hold time to active edge dsack t h(1) 0-ns r/w hold time after ds t h(2) c c. only applies if a read access is followed by a write access. r/w may stay high between 2 successive read accesses. 0-ns cs hold time after ds t h(3) b, d d. no timing constraint between the rising edges of cs and ds are defined, since no such relationship is defined in the mc68360 data sheet. cs is only latched at the beginning of an access. -- delay from ds to dsack driving t d(1) 020ns delay from clk to active edge dsack t d(2) 08ns delay from ds to inactive edge dsack t d(3) 07ns delay from dsack going inactive to dsack going in tristate t d(4) 5- delay from ds to dsack going in tristate t d(5) -20ns ds inactive pulse width t d(6) t cyc - response latency t d(7) tbd tbd delay from ds to d driving t d(8) 012ns delay from ds to d going in tristate t d(9) 012ns cs inactive pulse width t d(10) e e. between accesses to different peripherals t cyc - - 78 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 31. microprocessor interface: motorola mpc860 mode write cycle 1 1. see the lead description table on motorola mpc860 - host processor interface for the mapping to i/o leads. a rd/wr ts d ta t su(1) t su(2) t h(1) t h(5) clk t su(5) t d(6) t cyc t l t h t su(4) t h(4) t h(2) t d(1) cs t su(3) t h(3) t d(4) t d(2) t d(3) t d(5) - 79 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - a setup time before clk t su(1) a a. timing is relative to the rising edge of clk during which ts is asserted. 0-ns rd/wr setup time before clk t su(2) a, b b. only applies if a write access is preceded by a read access. rd/wr may stay low between 2 successive write accesses to the same peripheral. 0-ns cs setup time before clk t su(3) a, c c. cs may stay low between successive accesses to the same peripheral. 6-ns ts setup time before clk t su(4) 6-ns d setup time before clk t su(5) d d. timing is relative to next rising edge after the one during which ts is asserted. 0-ns a hold time after clk t h(1) e e. timing is relative to the rising edge of clk during which ta is asserted. 0-ns rd/wr hold time after clk t h(2) e, f f. only applies if a write access is followed by a read access. rd/wr may stay low between 2 successive write accesses to the same peripheral. 0-ns cs hold time after clk t h(3) e, c 0-ns ts hold time after clk t h(4) 4-ns d hold time after clk t h(5) e 0-ns delay from clk to ta driving t d(1) a 020ns delay from clk to active edge ta t d(2) g g. timing is relative to the rising edge before the one during which ta is asserted. 17ns delay from clk to inactive edge ta t d(3) e 17ns delay from ta going inactive to ta going in tristate t d(4) 5-ns delay from clk to ta going in tristate t d(5) e -20ns maximum response latency t d(6) tbd tbd - 80 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 32. microprocessor interface: motorola mpc860 mode read cycle 1 1. see the lead description table on motorola mpc860 - host processor interface for the mapping to i/o leads. a rd/wr ts d ta t su(1) t su(2) t h(1) t h(6) clk t su(6) t d(6) t cyc t l t h t su(4) t h(4) t h(2) t d(1) cs t su(3) t h(3) t d(3) t d(2) t d(4) t d(5) - 81 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - a setup time before clk t su(1) a a. timing is relative to the rising edge of clk during which ts is asserted. 0-ns rd/wr setup time before clk t su(2) a, b b. only applies if a read access is preceded by a write access. rd/wr may stay high between 2 successive read accesses to the same peripheral. 0-ns cs setup time before clk t su(3) a, c c. cs may stay low between successive accesses to the same peripheral. 6-ns ts setup time before clk t su(4) 6-ns a hold time after clk t h(1) d d. timing is relative to the rising edge of clk during which ta is asserted. 0-ns rd/wr hold time after clk t h(2) d, e e. only applies if a read access is followed by a write access. rd/wr may stay high between 2 successive read accesses to the same peripheral. 0-ns cs hold time after clk t h(3) c, d 0-ns ts hold time after clk t h(4) 4-ns delay from clk to ta driving t d(1) a 020ns delay from clk to active edge ta t d(2) f f. timing is relative to the rising edge before the one during which ta is asserted. 17ns delay from clk to inactive edge ta t d(3) d 17ns delay from ta going inactive to ta going in tristate t d(4) 5-ns delay from clk to ta going in tristate t d(5) d -20ns maximum response latency t d(6) tbd tbd d setup time before clk t su(6) d t cyc - hold time of d going in tristate to clk t h(6) d 112ns - 82 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 33. microprocessor interface: motorola mpc8260 local bus mode write cycle 1 1. see the lead description table on motorola mpc8260 local bus - host processor interface for the mapping to i/o leads. l_a lwr lcl_d lgta t su(1) t su(2) t h(1) t h(5) clk t su(5) t d(6) t cyc t l t h t h(2) t d(1) cs t su(3) t h(3) t d(5) t d(2) t d(3) t d(4) - 83 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - l_a setup time before clk t su(1) a a. timing is relative to the first rising edge of the access during which cs is asserted. 0-ns lwr setup time before clk t su(2) a, b b. only applies if a write access is preceded by a read access. lwr may stay low if 2 successive write accesses are done to the same peripheral. 0-ns cs setup time before clk t su(3) c c. cs may stay low between successive accesses to the same peripheral, as long as the other setup times are respected for the 2 nd access. if cs remains low between accesses, the second access starts after the first is terminated. 6-ns lcl_d setup time before clk t su(5) a 0-ns l_a hold time after clk t h(1) d d. timing is relative to the rising edge during which lgta is asserted. 0-ns lwr hold time after clk t h(2) d, e e. only applies if a write access is followed by a read access. lwr may stay low if 2 successive write accesses are done to the same peripheral. 0-ns cs hold time after clk t h(3) c, d 0-ns lcl_d hold time after clk t h(5) d 0-ns delay from clk to lgta driving t d(1) a 020ns delay from clk to active edge lgta t d(2) f f. timing is relative to the rising edge before the one during which lgta is asserted. 17ns delay from clk to inactive edge lgta t d(3) d 17ns delay from lgta going inactive to lgta going in tristate t d(4) 3*t cyc + 5 - ns delay from clk to lgta going in tristate t d(5) d 3*t cyc 3*t cyc + 20 ns maximum response latency t d(6) tbd tbd - 84 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 34. microprocessor interface: motorola mpc8260 local bus mode read cycle 1 1. see the lead description table on motorola mpc8260 local bus - host processor interface for the mapping to i/o leads. l_a lwr lcl_d lgta t su(1) t su(2) t h(1) t h(6) clk t su(6) t d(6) t cyc t l t h t h(2) t d(1) cs t su(3) t h(3) t d(5) t d(2) t d(3) t d(4) - 85 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 parameter symbol min typ max unit clk clock period t cyc 20 - ns clk clock low phase pulse width t l 0.4*t cyc - clk clock high phase pulse width t h 0.4*t cyc - l_a setup time before clk t su(1) a a. timing is relative to the first rising edge of the access during which cs is asserted. 0-ns lwr setup time before clk t su(2) a , b b. only applies if a read access is preceded by a write access. lwr may stay high if 2 successive read accesses are done to the same peripheral. 0-ns cs setup time before clk t su(3) c c. cs may stay low between successive accesses to the same peripheral, as long as the other setup times are respected for the 2nd access. if cs remains low between accesses, the second access starts after the first is termi- nated. 6-ns l_a hold time after clk t h1 d d. timing is relative to the rising edge during which lgta is asserted. 0-ns lwr hold time after clk t h(2) d , e e. only applies if a read access is followed by a write access. lwr may stay high if 2 successive read accesses are done to the same peripheral. 0-ns cs hold time after clk t h(3) c, d 0-ns delay from clk to lgta driving t d(1) a 020ns delay from clk to active edge lgta t d(2) f f. timing is relative to the rising edge before the one during which lgta is asserted. 17ns delay from clk to inactive edge lgta t d(3) d 17ns delay from lgta going inactive to lgta going in tristate t d(4) 3*t cyc + 5 - ns delay from clk to lgta going in tristate t d(5) d 3*t cyc 3*t cyc + 20 ns maximum response latency t d(6) tbd tbd d setup time before clk t su(6) d t- hold time of d going in tristate to clk t h(6) d 3*t cyc + 1 3*t cyc + 12 ns - 86 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 35. boundary scan timing parameter symbol min max unit tck clock period t cyc 50 ns tck clock duty cycle t pwh /t cyc 40 60 ns tms setup time to tck t su(1) 3.0 ns tms hold time after tck t h(1) 15 ns tdi setup time to tck t su(2) 3.0 ns tdi hold time after tck t h(2) 15 ns tdo delay from tck t d 4.0 20 ns trst pulse width t pw 50 ns tms tdi tdo t d(min) tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t cyc trst (input) t pw t d(max) - 87 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 operation sonet/sdh processing general the mapper and demapper blocks provide the sonet/sdh processing of the ethermap-12. the mapper maps and multiplexes a virtual concatenated payload into a vc-4/sts-3c/vc-3/sts-1 structure on the add telecom bus. conversely, the demapper demaps and demultiplexes a vc-4/sts-3c/vc-3/sts-1 structure from the drop telecom bus into a virtual concatenated payload. figure 36 shows a functional block diagram of the mapper and demapper blocks. figure 36. functional block diagram of the mapper/demapper vc-4/sts-3c poh monitor tu-3 pointer tracker/retimer vc-3/sts-1 poh monitor lo pointer low order poh monitor receive/drop telecom bus vc-4/sts-3c poh generator vc-3/sts-1/tug-3 crossconnect vc-3/sts-1 poh generator low order crossconnect low order poh generator transmit/add telecom bus drop telecom bus add telecom bus rx high order poh port rx low order poh port tx low order poh port tx high order poh port to rx virtual concatenation from tx virtual concatenation rx low order alarm indication port tx low order alarm indication port rx high order alarm indication port tx high order alarm indication port remote information (rx high order alarm indication port) remote information (rx low order alarm indication port) remote information (rx high order alarm indication port) vc-4/sts-3c crossconnect au-3/4pointer tracker/retimer - 88 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 37 presents a bi-directional functional model according to itu-t g.783 of the functionality made available through the mapper and demapper blocks (see itu-t g.806 for the terminology used). the telecom bus is represented as server layer to the s3/s4 high order path layers. . figure 37. functional model of the mapper/demapper te l e combus combus/s3_a combus/s4_a s3_tt sm_tt s3/sm_a s4/sm_a s4/s3_a s3_c sm_c s3-xv/s3-x_a s4-xv/s4-x_a sm-xv/sm-x_a s4_tt ri ri ri s4-xc/s4-x_a combus/s4- xc_a s4_c - 89 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 mapper block this block provides mapping and multiplexing for low order and high order tributaries (carrying ethernet framed data) into stm-4/sts-12 structures transmitted on the add side telecom bus. a vast assemblage of sonet/sdh rates and format mappings are supported as indicated below: sts-12c spe sts-12 / sts-9c spe sts-12 / sts-6c spe sts-12 / sts-3c spe sts-12 / sts-1 spe sts-12 / sts-1 / vt1.5 spe stm-4 / aug-4 / au-4-4c / vc-4-xc stm-4 / aug-4 / aug-1 / au-4 / vc-4 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tu-3 / vc-3 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-12s / vc-12 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-11s / vc-11 stm-4 / aug-4 / aug-1 / au-3 / vc-3 stm-4 / aug-4 / aug-1 / au-3 / vc-3 / tug-2 / tu-12 / vc-12 stm-4 / aug-4 / aug-1 / au-3 / vc-3 / tug-2 / tu-11 / vc-11 all supported mappings can be mixed according to the [g.707] multiplexing structure up to a total payload rate equivalent to one stm-4/sts-12 signal. high order path the tx mapper formats the vcs/spes into a stm-4/sts-12 structure. the pointer value carried in the h1 and h2 bytes is transmitted with a fixed value 0 or 522. the microprocessor writes the signal label, and the 16 or 64-byte value of the j1 message. the device provides either single-bit or three-bit rdi. local alarms, or the microprocessor, can generate the remote payload, server, or connectivity defect indications. the remote error indication (rei) is inserted from the bip-8 errors detected on the receive side, and bip-8 parity is generated for the b3 byte. control bits are provided to generate unequipped, supervisory unequipped and ais maintenance signals. control bits are also provided to insert rei and bip-8 errors in the g1/ b3 bytes for test purposes. the mapper complies with the latest itu/etsi/ansi standards and features regarding the generation of the high order path overhead bytes. these features include: j1 byte: 16 or 64 byte trail trace identifier. b3 byte: bip-8 calculation and insertion. c2 byte: signal label insertion. g1 byte: rei insertion (remote information from receive side). rdi insertion (remote information from receive side): single or three bit. optionally rdi generation for a minimum of 20 multiframes. h4 byte: optionally low order v1/v2 multiframe generation. optionally virtual concatenation multiframe generation. optionally lcas source state machine and control word generation. unequipped generation. supervisory unequipped generation. ais generation. - 90 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 tandem connection monitoring application is not supported. low order path low order vc/vt tributaries are formatted into an stm-4/sts-12 structure. the pointer value carried in the v1 and v2 bytes is transmitted with a fixed value of 78 for vt1.5 and 105 for tu-12. the microprocessor writes the signal label, and the value of the j2 message as a 16-byte message. the device provides either single-bit or three bit rdi using the v5 and k4 bytes. local alarms, or the microprocessor, can generate the remote payload, server, or connectivity defect indications. the remote error indication (rei) is inserted from the bip-2 errors detected on the receive side, and bip-2 parity is generated for the v5 byte. control bits are provided for generating unequipped, supervisory unequipped and ais maintenance signals. control bits are also provided to insert rei and bip-2 errors in the v5 byte for test purposes. a list of the vt/tu overhead byte generation functions is listed below: j2 byte 16 byte trail trace identifier. v5 and k4 (z7) byte rei insertion (remote information from receive side). rfi insertion microprocessor control. bip-2 calculation and insertion. rdi insertion (remote information from receive side): single or three bit. optionally rdi generation for a minimum of 20 multiframes. (extended) signal label insertion. 32-bit virtual concatenation multiframe generation. optionally lcas source state machine and control generation. unequipped channel generation. supervisory equipped generation. ais generation. tandem connection monitoring application is not supported. - 91 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 demapper block the demapper block provides the demapping and demultiplexing of the low order and high order tributaries from stm-4/sts-12 structures received on the drop side telecom bus. the same vast assemblage of formats that are supported by the mapper block are also supported by the demapper block as shown below: sts-12c spe sts-12 / sts-9c spe sts-12 / sts-6c spe sts-12 / sts-3c spe sts-12 / sts-1 spe sts-12 / sts-1 / vt1.5 spe stm-4 / aug-4 / au-4-4c / vc-4-xc stm-4 / aug-4 / aug-1 / au-4 / vc-4 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tu-3 / vc-3 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-12s / vc-12 stm-4 / aug-4 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-11s / vc-11 stm-4 / aug-4 / aug-1 / au-3 / vc-3 stm-4 / aug-4 / aug-1 / au-3 / vc-3 / tug-2 / tu-12 / vc-12 stm-4 / aug-4 / aug-1 / au-3 / vc-3 / tug-2 / tu-11 / vc-11 all supported mappings can be mixed according to the [g.707] multiplexing structure up to a total payload rate equivalent to one stm-4/sts-12 signal. high order path the rx demapper block performs high order (au-3/4/4-xc and tu-3) pointer processing and retiming. the pointer tracking process is based on etsi/itu-t standards, which also meets ansi requirements. pointer increments and decrements are counted. the high order poh bytes are processed and monitored for trail trace identifier mismatch, signal label mismatch, unequipped status, vc ais, bip-8 parity error detection and error counter, rei error counting, single-bit or three-bit remote defect indications (rdi), and loss of virtual concatenation or low order pointer multiframe. the received signal label can be retrieved, as well as the trail trace identifier of a selected channel. the rx demapper complies to the latest itu/etsi/ansi standards and features regarding the processing of the high order path overhead bytes. these features include: j1 byte: 16 or 64 byte trail trace identifier. b3 byte: bip-8 bit/block error counter option. c2 byte: signal label mismatch, unequipped, and vc ais detection. g1 byte: rdi detection, single or three bit. rei error counter. h4 byte: optionally low order v1/v2 multiframe monitoring. optionally virtual concatenation multiframe monitoring. optionally lcas sink state machine and control word retrieval. tandem connection monitoring application is not supported. - 92 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 low order path the rx demapper block performs low order pointer processing and retiming. the pointer tracking process is based on etsi/itu-t standards, which also meets ansi requirements. pointer increments and decrements are also counted, and the size bits are monitored for the correct value. the low order poh bytes are processed and monitored for trail trace identifier mismatch, signal label mismatch, unequipped status, vc ais, bip-2 parity error detection and error counter, rei error counting, single-bit or three-bit remote defect indications (rdi), and loss of virtual concatenation multiframe. the received (extended) signal label can be retrieved, as well as the trail trace identifier of a selected channel. the rx demapper complies to the latest itu/etsi/ansi standards and features regarding the processing of the low order path overhead bytes. these features include: j2 byte: 16 byte trail trace identifier. v5 and k4/z7 byte: rdi detection, single or three bit. rei error counter. rfi detection. bip-2 bit/block error counter option. signal label mismatch, unequipped, and vc ais detection. 32-bit virtual concatenation multiframe monitoring. optionally lcas sink state machine and control word retrieval. tandem connection monitoring application is not supported. - 93 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 transmit high order path termination (vc-3/vc-4/vc-4-xc/sts-1/sts-nc poh generator) general the ethermap-12 optionally provides transmit high order path termination functions for one sts-12c spe/vc- 4-4c, one sts-9c spe/vc-4-3c, two sts-6c spe/vc-4-2cs, four sts-3c-spe/vc-4s and twelve sts-1 spe/vc-3s. j1 the transmitted j1 path trace message can be written by the microprocessor for transmission into the up_j1messagebytes ram at address (tbd). the device supports 16 or 64 byte long repeating messages. the length can be selected via the j1_length64 register, i.e., bit (tbd) at address (tbd). b3 the b3 is calculated and transmitted for each spe/vc. for test purposes the ethermap-12 supports a b3 error mask in the poh ram, at address (tbd). when the b3_masking register, bit (tbd) at address (tbd) is set, the calculated b3 is exor ? ed with the b3 error mask before being inserted into the signal. c2 the c2 signal label can be written by the microprocessor for transmission into the c2 position of the poh ram at address (tbd). the ethermap-12 also has the option to source an unequipped signal by setting the forceuneq register (bit tbd at address tbd) or a supervisory unequipped spe/vc by setting the forcesupuneq register (bit tbd at address tbd). g1 the received b3 errors are automatically inserted into the g1 byte as path rei. the ethermap-12 has on option to transmit either a single bit path rdi or an enhanced 3-bit path rdi. selection is made via the onebitrdi register (bit tbd at address tbd). the transmitted g1 bytes can be generated from local alarm conditions or derived from the alarm indication port interface. the selection is made per high order path timeslot on the high order alarm indication port interface via the selectinterface register at address (tbd). see the high order alarm indication port interface section for the time slot assignment. when the unidirectional option is active by setting the g1_unidirectional register (bit tbd at address tbd), all transmitted remote information is set to zero. tbd selectinterface 0 rdi and rei generated from local alarm conditions. 1 rdi and rei derived from high order alarm indication port interface. - 94 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 h4 the h4 byte can be written by the microprocessor into the poh ram at address (tbd), or by the high order poh port interface for transmission, or it can be selected to carry the v1/v2 multiframe in case the spe/vc is substructured into low order tu/vts. it can also be selected to carry the virtual concatenation multiframe and control packets in case high order virtual concatenation is active for this spe/vc. this selection is made via the h4_control register, bits (tbd) at address (tbd): f2, f3, k3, and n1 the f2, f3, k3, and n1 bytes can be written by the microprocessor into the poh ram, at address (tbd), or by the high order poh port interface for transmission. these values are static and are not acted upon by the ethermap-12 transmit logic. the source can be selected via the f2_control, f3_control, k3_control and n1_control registers (bits tbd at address tbd): a value of 0 selects the poh ram, a value of 1 selects the poh port. receive high order path termination (vc-3/vc-4/vc-4-xc/sts-1/sts-nc poh monitor) general the ethermap-12 optionally provides receive high order path termination functions for one sts-12c spe/vc- 4-4c, one sts-9c spe/vc-4-3c, two sts-6c spe/vc-4-2cs, four sts-3c-spe/vc-4s and twelve sts-1 spe/vc-3s. the received poh bytes are always forwarded to the receive high order poh port interface and written to the receive high order poh ram at address (tbd). j1 both 16 and 64 byte messages can be received. the expected j1 path trace message can be configured at address (tbd). the received j1 path trace is compared with the microprocessor written expected j1 path trace. if a mismatch occurs between received and expected j1 path trace, a trace identifier mismatch defect (dtim) is declared. an all-zero path trace is also reported to allow detection of an unequipped signal versus a supervisory unequipped signal. the microprocessor can retrieve the value of the received j1 path trace of one vc-4/sts-3c and of one vc-3/sts-1 path termination at a time. bit tbd bit tbd h4_control 0 0 insert h4 from the poh ram, e.g. for an unstructured, non-virtual concatenated vc- 4/sts-3c. 0 1 insert h4 from the high order poh port. 1 0 pass the multiframe and control word for a virtual concatenated vc-3/sts-1. 1 1 generate the v1/v2 multiframe for vc-3/vc-4/sts-1 spe substructured into lo tu/vt ? s. address register description tbd accepted 64 byte trace message tbd j1_report_enable enable reporting of the accepted j1 trace message for the j1_report_channel. - 95 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the number of trace message multiframes to set or reset the tim defect is configurable via registers j1_nrofframestosettim (bits tbd at address tbd) and j1_nrofframestoresettim (bits tbd at address tbd). b3 performance monitor counters are provided for the b3 errors and b3 block errors. optionally, the burst error degraded signal defect can be detected. the threshold values and interval times are configurable per high order path via registers b3_setthreshold, b3_clearthreshold, b3_setnrofintervals and b3_clearnrofintervals at address (tbd). c2 unequipped detection (duneq) and vc ais detection (dais) is performed on the incoming c2 byte. the expected c2 signal label can be written by the microprocessor at address (tbd). if a mismatch occurs between the received c2 and the expected c2, a payload mismatch defect (dplm) is declared. the accepted c2 value is written to the on-chip ram for retrieval by the microprocessor at address (tbd). g1 a performance monitoring counter is provided for the path rei. the g1 byte is monitored for the presence of single bit or enhanced path rdi. h4 the h4 byte is written to the on-chip ram for retrieval by the microprocessor. it can be optionally monitored for the v1/v2 multiframe in case the spe/vc is substructured into low order tu/vts, or the virtual concatenation multiframe in case high order virtual concatenation is active for this spe/vc. the selection is made per high order path via the h4_multiframetype register (bits tbd at address tbd). f2, f3, k3, and n1 the f2, f3, k3, and n1 are written to the on-chip high order poh ram for retrieval by the microprocessor. tbd j1_report_channel select the vc-4/sts-3c spe resp vc-3/sts-1 spe channel for which the j1 accepted trace message is retrieved. tbd j1_stable_1 a constantly repeating single j1 byte has been detected. tbd j1_stable_16 a 16-byte j1 trace message has been detected. tbd j1_stable_64 a 64-byte j1 trace message has been detected. h4_multiframetype 00 disable monitoring of h4. 01 monitor the v1/v2 multiframe for a vc-3/vc-4/sts-1 spe substructured into low order tu/vts. 10 monitor the virtual concatenation multiframe. 11 reserved. address register description - 96 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 high order poh port interface all received high order poh bytes are output on the receive high order poh port interface. the transmit high order poh port interface allows inserting most high order poh byte into the high order poh. j1 and c2 cannot be selected from the transmit high order poh port interface, while the b3 bip-8 is used as error mask on the calculated bip-8 for test purposes. each interface consists of clock, data, data enable, address and address enable lines. the address is a 8-bit word with following format: high order alarm indication port interface the high order alarm indication port interface transports the remote information (ri) from the high order poh sink/monitor to the poh source/generator. the remote information consists of the rei and (enhanced) rdi values to insert by the poh generator. the high order poh monitor blocks multicast the remote information of all high order path channels to the high order poh generator blocks and the receive high order alarm indication port interface. the high order poh generator blocks can select per high order path channel if the remote information is taken from the transmit high order alarm indication port interface, or the internal remote information provided by the high order poh monitor blocks. each interface consists of a clock, data and start of frame line. a start of frame pulse coincides with the first bit of the high order alarm indication port data frame. a7-a4 a3a2a1a0 channel number0000 j1 0001 b3 0010 c2 0011 g1 0100 f2 0101 h4 0110 f3 0111 k3 1000 n1 - 97 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 each high order alarm indication port data frame consists of 16 timeslots of 32 bits per timeslot: the first 12 time slots are assigned to vc-3/sts-1 remote information, the last 4 time slots to vc-4/sts-3c remote information: frame x x+1 timeslot 0 1 ... 15 ... bit number 31 30 ... 10 31 30 ... 1 0 ... 31 30 ... 1 0 ... timeslot assigned to 0vc3/sts-1 #1 1vc3/sts-1 #2 2vc3/sts-1 #3 3vc3/sts-1 #4 4vc3/sts-1 #5 5vc3/sts-1 #6 6vc3/sts-1 #7 7vc3/sts-1 #8 8vc3/sts-1 #9 9vc3/sts-1 #10 10 vc3/sts-1 #11 11 vc3/sts-1 #12 12 vc-4/sts-3c #1 13 vc-4/sts-3c #2 14 vc-4/sts-3c #3 15 vc-4/sts-3c #4 - 98 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 each 32-bit timeslot has a field for the rei and rdi. a valid flag indicates if the value in a field is valid and needs to be processed. invalid values are ignored. sts-1/au-3/au-4 pointer generation in add bus master mode, the pointer value can be configured to be any value from 0 to 782. tu-3 pointer generation the tu-3 pointer has a fixed value of 0. tu-3 pointer tracking the incoming negative and positive tu-3 pointer adjustments are counted for performance monitoring. the lop and pointer ais defects are detected. vc-3/sts-1/tug-3 cross connect the vc-3/sts-1/tug-3 timeslots can be interchanged. each tsi output vc-3/sts-1/tug-3 timeslot can be configured to connect to any tsi input timeslot (sourceslot) or to send an unequipped (forceuneq) or ais (forceais) signal. tu/vt pointer tracking the incoming negative and positive pointer adjustments are counted for performance monitoring. the lop and pointer ais defects are detected. the v1, v2, and v4 bytes are written to the on-chip ram for retrieval by the microprocessor (v1 ram at tbd). tu/vt pointer generation the vt1.5/tu-11 pointer of the added vt1.5/vc-11s has a fixed value equal to 78. the vt2/tu-12 pointer of the added vt2/vc-12s has a fixed value equal to 105. bit number name description 31 rei-valid rei value in bits 30..27 is valid. 30..27 rei rei value 26 reserved 25 rdi-valid rdi values in bits 24..22 are valid 24 rdi-s enhanced rdi server failure, contributes to single bit rdi 23 rdi-c enhanced rdi connectivity failure, contributes to single bit rdi 22 rdi-p enhanced rdi path failure 21..4 reserved 3..0 crc-4 crc-4 over bits 31..4 - 99 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 low order cross connect the low order timeslots can be interchanged. each low order tsi output timeslot can be configured to connect to any tsi input timeslot or to send an unequipped (forceuneq) or ais (forceais) signal. cross connects are made by writing the appropriate value into the mapram_data cross connect map. this array of 336 elements is indexed by the output channel number, and its value represents the input channel number to be connected to this output channel. the cross connect map consists of two banks of 336 elements. the cross connect hardware reads the information from the active bank, while the software can only write to the inactive bank. when a new configuration is written to the inactive bank, both banks can be swapped. software can select which of the banks is visible for reading. transmit low order path termination (low order poh generator) general the ethermap-12 provides transmit low order path termination functions for up to 336 vt1.5-spe/vc-11s or 252 vt2-spe/vc-12s. the low order poh generators are numbered according to the (b, 0) klm numbering: channel = (b-1)*84+(k-1)*28+(l-1)*4+(m-1) j2 the j2 path trace can be written by the microprocessor for transmission as a 16 byte long repeating message in the transmit low order poh ram at address (tbd). bip-2 the v5 bip-2 is calculated and transmitted for each vt/vc. for test purposes, the ethermap-12 supports a bip-2 error mask in the transmit low order poh ram, at address (tbd). when the bip2_error register, bit (tbd) at address (tbd), is set, the calculated bip-2 is exor ? ed with the bip-2 error mask before being inserted into the v5 byte. channel vc-4/sts-3c # assigned to low order #klm 0 0 vt1.5/vc-12 #111 1 vt1.5/vc-12 #112 2 vt1.5/vc-12 #113 3 vt1.5 #114 4 vt/vc-12 #121 ... ... 82 vt1.5/vc-12 #373 83 vt1.5 #374 84 1 vt1.5/vc-12 #111 ... 334 3 vt1.5/vc-12 #373 335 vt1.5 #374 - 100 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 signal label both the v5 signal label (in the transmit low order poh ram at address tbd) and the k4 extended signal label (ext_signallabel register at address tbd) can be written by the microprocessor for transmission. the v5 signal label must be set to ? 101 ? to activate the generation of the k4 bit 1 mfas and extended signal label. the ethermap-12 also has the option to source an unequipped signal or a supervisory unequipped vt/vc through the senduneq and uneqselect registers at address (tbd). rei/rdi the received v5 bip-2 errors are automatically inserted into the v5 path rei. the ethermap-12 has an option to transmit either a single bit v5 path rdi, or an enhanced 4-bit v5/k4 path rdi. the transmitted rei/rdi can be generated from local alarm conditions or derived from the alarm indication port interface. when the unidirectional option is active, all transmitted remote information is set to zero. k4 bit 2 the k4 bit 2 can be written by the microprocessor or by the high order poh port interface for transmission, or it can be selected to carry the virtual concatenation multiframe and control packets in case low order virtual concatenation is active for this vt/vc. in the latter case, the extended signal label in k4 bit 1 has to be activated to generate the mfas word (see ? signal label ? on page 100 ). the source for the k4 bit 2 can be selected per low order channel through register lo_vc_source, bits (tbd) at address (tbd). v5 rfi, and n2 the v5 rfi bit, n2 byte can be written by the microprocessor or by the low order poh port interface for transmission. this value is static and is not acted upon by the ethermap-12 transmit logic. receive low order path termination (low order poh monitor) general the ethermap-12 provides receive low order path termination functions for up to 84 vt1.5-spes or 63 vc- 12s for each sts-3-spe or vc-4. like the low order poh generators, the low order poh monitors are numbered according to the (b,0) klm numbering: channel = (b-1)*84+ (k-1)*28+(l-1)*4+(m-1) senduneq bit tbd uneqselect bit tbd 0 x source an equipped vc/vt. 1 0 source an unequipped vc/vt. 1 1 source a supervisory unequipped vc/vt bit (tbd) bit (tbd) lo_vc_source 0 0 insert k4 bit 2 from the poh ram. 0 1 insert k4 bit 2 from the high order poh port. 10reserved 1 1 pass the multiframe and control word for a virtual concatenated vc-12/vt1.5 spe. - 101 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the received poh bytes are always forwarded to the receive low order poh port interface and written to the receive low order poh ram at address (tbd). j2 the ethermap-12 supports 16 byte j2 trace messages. the received j2 path trace message can be compared with a microprocessor written expected j2 path trace at address (tbd). if a mismatch occurs between received and expected j2 path trace, a trace identifier mismatch defect (dtim) is declared. an all-zero path trace is also reported to allow detection of an unequipped signal versus a supervisory unequipped signal. the microprocessor can retrieve the value of the received j2 path trace of one low order path termination at a time. the number of trace message multiframes to set or reset the tim defect is configurable via registers j2_nrofframestosettim (bits tbd at address tbd) and j2_nrofframestoresettim (bits tbd at address tbd). bip-2 performance monitor counters are provided for the v5 bip-2 errors and v5 bip-2 block errors. optionally the burst error degraded signal defect can be detected. the threshold values and interval times are configurable per low order path via registers bip2_deg_setthreshold, bip2_deg_clearthreshold, bip2_deg_setnrofintervals and bip2_deg_clearnrofintervals at address (tbd). signal label unequipped detection (duneq) and vc ais detection (dais) is performed on the incoming v5 signal label. the expected v5 signal label and the expected k4 extended signal label can be written by the microprocessor. if a mismatch occurs between the received and the expected (extended) signal label, a payload mismatch defect (dplm) is declared. the accepted v5 signal label and k4 extended signal label values are written to the on-chip ram for retrieval by the microprocessor. the number of (multi-)frames to accept a tsl or extended tsl value is configurable via registers tsl_nrofintervals (bits tbd at address tbd) and etsl_nrofintervals (bits tbd at address tbd). address register description (tbd) accepted 16 byte trace message (tbd), bit tbd j2_report_enable enable reporting of the accepted j2 trace message for the j2_report_channel. (tbd), bits tbd j2_report_channel select the vt/vc channel for which the j2 accepted trace message is retrieved. (tbd), bit tbd j2_stable_1 a constantly repeating single j2 byte has been detected. (tbd), bit tbd j2_stable_16 a 16-byte j2 trace message has been detected. address register description tsl_accepted accepted v5 trail signal label. etsl_accepted accepted k4 extended trail signal label. tsl_expected expected v5 trail signal label. etsl_expected expected k4 extended trail signal label. - 102 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 rei/rdi/rfi a performance monitoring counter is provided for the path rei. the v5/k4 bytes are monitored for the presence of single bit or enhanced path rdi. the v5 byte is monitored for the presence of rfi k4 bit 2 the k4 bit 2 can be optionally monitored for the virtual concatenation multiframe in case lower order virtual concatenation is active for this spe/vc. n2 the n2 byte is written to the on-chip ram for retrieval by the microprocessor. low order poh port interface all received low order poh bytes of all 63/84 timeslots are output on the receive low order poh port interface. the transmit low order poh port interface allows inserting most low order poh byte into the low order poh. j2 and the v5/k4 signal label cannot be selected from the transmit lo poh port interface, while the v5 bip-2 field is used as error mask on the calculated bip-2 for test purposes. each interface consists of clock, data, data enable, address and address enable lines. the address is a 12-bit word with following format: the low order time slots are numbered according to the (b,0) klm numbering: timeslot = (b-1)*84+(k-1)*28+(l-1)*4+(m-1) a11 a10-a2 a1 a0 0 (reserved) timeslot number (range 0..335) 00 v5 01 j2 10 n2/z6 11 k4/z7 channel vc-4/sts-3c #(b,0) assigned to low order #klm 0 0 vt1.5/vc-12 #111 1 vt1.5/vc-12 #112 2 vt1.5/vc-12 #113 3 vt1.5 #114 4 vt/vc-12 #121 ... ... 82 vt1.5/vc-12 #373 83 vt1.5 #374 84 1 vt1.5/vc-12 #111 ... 334 3 vt1.5/vc-12 #373 335 vt1.5 #374 - 103 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 low order alarm indication port interface the low order alarm indication port interface transports the remote information (ri) from the low order poh sink/monitor to the poh source/generator. the remote information consists of the rei and (enhanced) rdi values to insert by the poh generator. the low order poh monitor blocks multicast the remote information of all low order channels to the low order poh generator blocks and the receive low order alarm indication port interface. the low order poh generator blocks can select per low order channel if the remote information is taken from the transmit low order alarm indication port interface or the internal remote information provided by the low order poh monitor blocks. each interface consists of a clock, data and start of frame line. a start of frame pulse coincides with the first bit of the low order alarm indication port data frame. each low order alarm indication port data frame consists of 336 timeslots of 16 bits per timeslot: the low order time slots are numbered according to the (b,0) klm numbering: timeslot = (b-1)*84+ (k-1)*28+(l-1)*4+(m-1) each 16-bit timeslot has a field for the rei and rdi. a valid flag indicates if the value in a field is valid and needs to be processed. invalid values are ignored. frame x x+1 timeslot 0 1 ... 335 ... bit number 15 14 ... 10 15 14 ... 1 0 ... 15 14 ... 1 0 ... channel vc-4/sts-3c #(b,0) assigned to low order #klm 0 0 vt1.5/vc-12 #111 1 vt1.5/vc-12 #112 2 vt1.5/vc-12 #113 3 vt1.5 #114 4 vt/vc-12 #121 ... ... 82 vt1.5/vc-12 #373 83 vt1.5 #374 84 1 vt1.5/vc-12 #111 ... 334 3 vt1.5/vc-12 #373 335 vt1.5 #374 bit number name description 15 rei-valid rei value in bits 30..27 is valid. 14 rei rei value 13 rdi-valid rdi values in bits 24..22 are valid 12 rdi-s enhanced rdi server failure, contributes to single bit rdi 11 rdi-c enhanced rdi connectivity failure, contributes to single bit rdi 10 rdi-p enhanced rdi path failure 9..4 reserved 3..0 crc-4 crc-4 over bits 15..4 - 104 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 virtual concatenation and lcas the ethermap-12 device takes a contiguous piece of ethernet bandwidth and breaks it up into a number of individual spe/vc which travel independently through the sonet/sdh network and are reassembled at their destination back into the contiguous piece of ethernet bandwidth. the ethermap-12 also performs the converse, by taking the spe/vc that it has received from a sending device and reassembling it back into a contiguous piece of ethernet bandwidth. two tremendous advantages are immediately obvious: 1) since the ethernet traffic is traveling through the network in a standard size spe/vc, only the equipment at the end points needs to be changed. 2) granularity of bandwidth used can be variable and in increments of the spe/vc that is used. this is useful for the transport of payloads, such as ethernet, which do not efficiently fit into one of the standard spe/vc. the ethermap-12 device also supports lcas (link capacity adjustment scheme). this is a mechanism where the allocated bandwidth for an ethernet link can be dynamically reconfigured without causing any hits on to the existing traffic flow. the sections below will describe in greater detail how the ethermap-12 performs virtual concatenation. - 105 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 low order virtual concatenation without lcas 1 in sonet mode ethernet traffic is transported in vt1.5-xv-spe as follows: figure 38. vt1.5-xv-spe structure the vt1.5-xv-spe payload capacity consists of ethernet traffic which has been encapsulated in one of five ways: gfp, laps, lapf, ppp or transparent hdlc. more will be said about these encapsulation methods in following sections. in sdh mode, ethernet traffic is transported in vc-12-xv as shown below or in a vc-3-xv as shown in figure 45 . note, a vc-3 is considered high order if carried in an au-3, and low order if carried in a tug-3; in this case the vc-3s are mapped to a tug-3 as shown in figure 40 . also note that the ethermap-12 has the capability to map the vc-3s to either a tug-3 or au-3 just like for the vt1.5-xv-spe case, the vc-12xv payload capacity consists of ethernet traffic which has been encapsulated using gfp, laps, lapf, ppp or transparent hdlc. 1. note: in itu-t sdh a vc-3 can either be high order (au-3/sts-1) or low order (tu-3). in the ethermap-12 data sheet high order and low order refers to the type of path overhead bytes rather than the order of the path in the mul- tiplexing hierarchy. though both low and high order vc-3 mapping is supported, vc-3 operation will be covered in the high order path sections (h4), while the low order sections only cover vc-11/vt1.5 and vc-12/vt2 (k4/z7). 1 2 x xx25 vt1.5-xv-spe payload capacity 1 4 1 vt1.5-spe # x 1 4 500 s 26 v5 j2 z6 z7 1 vt1.5-spe # 1 1 4 500 s 26 v5 j2 z6 z7 vt1.5-xv-spe - 106 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 . figure 39. vc-11-xv structure once the ethermap-12 has broken up the ethernet payload into vc-12 or vt1.5-spe they are then multiplexed into their respective sdh or sonet frame structures as shown below. figure 40. lo sdh multiplexing structure 1 supported by the ethermap-12 1 vc-12 # x 1 4 500 s 35 v5 j2 n2 k4 1 2 x xx34 c-12-xc payload capacity 1 4 1 vc-12 # 1 1 4 500 s 35 v5 j2 n2 k4 vc-12-xv tug-3 tug-2 tu-12 vc-4 vc-12 from c-12-xc multiplexing aligning mapping pointer processing x3 x7 x3 payload capacity - 107 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 41. lo sdh multiplexing structure 3 supported by the ethermap-12 figure 42. lo sdh multiplexing structure 2 supported by the ethermap-12 figure 43. lo sonet multiplexing structure supported by the ethermap-12 tug-3 tu-3 vc-4 vc-3 from c-3-xc multiplexing aligning mapping pointer processing x3 x1 payload capacity tug-2 tu-12 vc-3 vc-12 from c-12-xc multiplexing aligning mapping pointer processing x7 x3 payload au-3 aug x3 capacity vt1.5 sts-1- vt1.5- fromvt1.5-spe-xv multiplexing aligning mapping pointer processing x28 payload capacity spe spe sts-1 sts-3 x3 - 108 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 low order virtual concatenation with lcas when using low order virtual concatenation in sonet/sdh mode, every low order virtual concatenation group (vcg) can be independently configured to optionally operate in lcas mode. low order virtual concatenation can be used without lcas, but lcas requires low/high order virtual concatenation. the low order virtual concatenation lcas control packet definition and format is specified in the itu-t g.707/y.1322 standard. the lcas protocol is specified in the itu-t g.7042/y.1305 standard. for sonet mode, the lcas control packet is resident in the z7 [bit 2] poh byte. for sdh mode, the lcas control packet is resident in the k4 [bit 2] poh byte. during initialization/normal operation, the ethermap-12 device provides support for management and re- allocation of member resources between lcas and non-lcas modes for use by multiple low order vcgs. in addition, general add and remove operations are supported using single high level messages. in the transmit direction, for every member of a low order vcg operating in lcas mode, the ethermap-12 device provides individual source side lcas hardware-based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: prbs generation for the group identification (gid) bit field. crc-3 generation. lcas sequence indicator (sq) field generation. lcas control (ctrl) field generation. inter-member messages during add/remove operations. for each transmit low order vcg in lcas mode, selection of a low order member, in the receive direction, that is carrying the member status (mst) and re-sequence acknowledge (rs-ack) information. termination of mst and rs-ack information from respective sink side lcas state machine. configurable low order per-member and per-vcg time-out counters for detection of failure during add and remove operations. alarm generation to indicate lcas source side state machine status. in the receive direction, for every member of a low order vcg operating in lcas mode, the ethermap-12 device provides for individual sink side lcas hardware based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: group identification (gid) field mismatch detection. crc-3 check. lcas sequence indicator (sq) field processing. lcas control (ctrl) field processing. generation of mst and rs-ack status information. detection and processing of trail signal fail (tsf) conditions. for each receive low order vcg in lcas mode, selection of a transmit side low order vcg that is used to transport the member status (mst) and re-sequence acknowledge (rs-ack) information. alarm generation to indicate lcas sink side state machine status. - 109 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 high order virtual concatenation without lcas in sonet mode ethernet traffic is transported in sts-1-xv-spe or in a sts-3c-spe. the sts-1-xv-spe structure is shown in the figure 44 . the sts-1-xv-spe payload capacity or the sts-3c-spe data consists of ethernet traffic which has been encapsulated in one of five ways: gfp, laps, lapf, ppp or transparent hdlc. figure 44. sts-1-xv-spe structure sts-1-xv-spe j1 b3 c2 g1 f2 h4 z3 z4 n1 1 1 9 j1 b3 c2 g1 f2 h4 z3 z4 n1 1 1 9 30 59 87 sts-1 spe #1 sts-1 spe #x 125 s 125 s fixed stuff 1 1 9 xx84 sts-1-xv-spe payload capacity x - 110 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 in sdh mode ethernet traffic is transported in vc-3-xv or in vc-4. just like for the sts-1-xv-spe payload capacity the payload capacity for the vc-3-xv and vc-4 consists of ethernet traffic which has been encapsulated using gfp, laps, lapf, ppp or transparent hdlc. the vc-3-xv structure is shown below. note, a vc-3 is considered high order as long as it is not carried in a tug-3. figure 45. vc-3-xv structure vc-3-xv j1 b3 c2 g1 f2 h4 z3 z4 n1 1 1 9 j1 b3 c2 g1 f2 h4 z3 z4 n1 1 1 9 85 vc-3 #1 vc-3 #x 125 s 125 s 1 1 9 xx84 c3-xc x 125 s - 111 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 once the ethermap-12 has broken up the ethernet payload into vc-3 or sts-1-spe they are then multiplexed into their respective sdh or sonet frame structures as shown below. notice that for the vc-3 structure that no stuff columns exist. however, when inserted into the au-3, stuff columns are added so that the vc-3 ends up resembling an sts-1-spe. figure 46. ho sdh multiplexing structure supported by the ethermap-12 figure 47. ho sonet multiplexing structure supported by the ethermap-12 aug-3 au-3 vc-3 from c-3-xc multiplexing aligning mapping pointer processing x3 payload capacity sts-1 sts-3 sts-1- from sts-1-spe-xv multiplexing aligning mapping pointer processing x3 payload capacity spe - 112 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 high order virtual concatenation with lcas when using high order virtual concatenation in sonet/sdh mode, every high order virtual concatenation group (vcg) can be independently configured to optionally operate in lcas mode. high order virtual concatenation can be used without lcas, but lcas requires low/high order virtual concatenation. the high order virtual concatenation lcas control packet definition and format is specified in the itu-t g.707/y.1322 standard. the lcas protocol is specified in the itu-t g.7042/y.1305 standard. for both sonet and sdh modes, the lcas control packet is resident in the h4 poh byte. during initialization/normal operation, the ethermap-12 device provides support for management and re- allocation of member resources between lcas and non-lcas modes for use by multiple high order vcgs. in addition, general add and remove operations are supported using single high level messages. in the transmit direction, for every member of a high order vcg operating in lcas mode, the ethermap-12 device provides for individual source side lcas hardware-based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: prbs generation for the group identification (gid) bit field. crc-8 generation. lcas sequence indicator (sq) field generation. lcas control (ctrl) field generation. inter-member messages during add/remove operations. for each transmit high order vcg in lcas mode, selection of a high order member, in the receive direction, that is carrying the member status (mst) and re-sequence acknowledge (rs-ack) information. termination of mst and rs-ack information from respective sink side lcas state machine. configurable high order per-member and per-vcg time-out counters for detection of failure during add and remove operations. alarm generation to indicate lcas source side state machine status. in the receive direction, for every member of a high order vcg operating in lcas mode, the ethermap-12 device provides for individual sink side lcas hardware based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: group identification (gid) field mismatch detection. crc-8 check. lcas sequence indicator (sq) field processing. lcas control (ctrl) field processing. generation of mst and rs-ack status information. detection and processing of trail signal fail (tsf) conditions. for each receive high order vcg in lcas mode, selection of a transmit side high order vcg that is used to transport the member status (mst) and re-sequence acknowledge (rs-ack) information. alarm generation to indicate lcas sink side state machine status. - 113 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 configuration general the virtual concatenation of 8 ethernet lines within 8 vcgs can be performed with the ethermap-12. for both transmit and receive, it is possible to configure the design in low order, high order, mixed high order/low order with lcas or non lcas on a per vcg basis. the following paragraphs explain how to configure the virtual tributaries and how to extract status information from the device. note: a coherency is necessary between the configuration of the virtual concatenation part of the design and the mapper configuration (for example: high order virtual concatenation with high order mapping). all configu- ration bits which are defined with ? bklm ? indication ( [1..4][1..3][1..7][1..4] ) are dedicated to the low order con- figuration which is shown in the following table (correspondence between channel number and bklm). use the following procedure to add/remove members to a vcg in non-lcas mode: transmit vcg 1) the member to be added must be first assigned to global pool of resources. this is done by setting the control bits ctlopool_x (case of a tx low order member), cthopool_x (tx high order) to 00. 2) perform a soft reset of the vcg affected (set tx_resetsx register to 0x91). 3a) add the member by placing it into the non-lcas pool of resource. this is done by setting the control bits ctlopool_x or cthopool_x to 01. the sequence indicator and vcg must be assigned to the member. - or - 3b) remove the member by placing it into the global pool state. 4) clear the soft reset per channel by writing 0x00 in tx_resetsx. receive vcg 1) the member to be added must be first assigned to global pool of resources. this is done by setting the control bits crlopool_x (rx low order), crhopool_x (rx high order) to 00. 2) perform a soft reset of the mac corresponding to the vcg by setting to 1 the reset tx function (bit tbd) (in the address tbd for mac0). channel vc-4/sts-3 #(b,0) assigned to low order #klm 0 0 vt1.5/vc-12 #111 1 vt1.5/vc-12 #112 2 vt1.5/vc-12 #113 3 vt1.5 #114 4 vt/vc-12 #121 ... ... 82 vt1.5/vc-12 #373 83 vt1.5 #374 84 1 vt1.5/vc-12 #111 ... 334 3 vt1.5/vc-12 #373 335 vt1.5 #374 - 114 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 3) perform a soft reset of the vcg affected (set rx_resetsx register to 0x91). 4a) add the member by placing it into the non-lcas pool of resources. this is done by setting the control bits crlopool_x or crhopool_x to 01. the sequence indicator and vcg must be assigned to the member. - or - 4b) remove the member by placing into the global pool state. 5) clear the soft reset of the mac by clearing the reset tx function (bit tbd in the address tbd for mac0). 6) clear the soft reset per channel by writing 0x00 in rx_resetsx. - 115 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 differential delay compensation the ethermap-12 performs differential delay compensation, for the containers included in a given virtual concatenation group. this supports the scenario where the virtually concatenated containers travel different paths in the sonet/sdh network, and therefore are received by the ethermap-12 with a time offset. the mutliframe indicator field (mfi) is used for differential delay detection. mfi is located in the h4 byte (for high order virtual concatenation) or in the k4/z7 byte (for low order virtual concatenation). for each virtual concatenation group (vcg_x, x = 0 - 7), two registers are provided. see below. maximum differential delay allowed register rmaxdelvcg_x is used to configure the maximum differential delay value allowed amongst the members of a virtual concatenation group (vcg_x). the maximum value that can be configured for both low order virtual concatenation (lo vcat) and high order virtual concatenation (ho vcat) is 64 ms. low order in lo vcat, only bits (tbd) of rmaxdelvcg_x are used. the value is configured in steps of 16 ms. table 1 shows the five values allowed: table 1: configuration of rmaxdelvcg_x in low order vc high order in ho vcat, bits (tbd) of rmaxdelvcg_x are used. the value is configured in steps of 125 s. table 2 shows the 512 values allowed: table 2: configuration of rmaxdelvcg_x in high order vc configuration of rmaxdelvcg_x multiple of 16 ms resulting maximum delay allowed 0x0000 0 x 16 ms 0 ms 0x0080 1 x 16 ms 16 ms 0x0100 2 x 16 ms 32 ms 0x0180 3 x 16 ms 48 ms 0x0200 4 x 16 ms 64 ms configuration of rmaxdelvcg_x multiple of 125 s resulting maximum delay allowed 0x0000 0 x 125 s 0 ms 0x0001 1 x 125 s 125 s .... ... .... 0x0180 384 x 125 s48 ms .... ... .... 0x0200 512 x 125 s64 ms - 116 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 maximum differential delay detected register rdifdelvcg_x reports the maximum differential delay detected among the members of a given virtual concatenation group (vcg_x). the maximum delay that can be detected is 128 ms. low order in lo vcat, bits (tbd) of rdifdelvcg_x represent the maximum differential delay detected among the low order members of a vcg_x. the register has a granularity of 16 ms: a value of 0001 hex represents a delay of 16 ms. the maximum allowed value is 8, corresponding to 128 ms. if the delay is higher than 128 ms, then bit (tbd) of rdifdelvcg_x is set, indicating ethermap-12 is not able to compute such a differential delay, and further, bits (tbd) of rdifdelvcg_x contain invalid information. further more in lo vcat, when the reported differential delay is found to be greater than one configured in the rmaxdelvcg_x register, an alarm, aloloa_x, is generated (i.e., at a per vcg_x level). high order in ho vcat, bits (tbd) of rdifdelvcg_x represents the maximum differential delay detected among the members of a vcg_x. the register has a granularity of 125 s: a value of 0001 hex represents a delay of 125 s. the maximum allowed value is 1024, corresponding to 128 ms. if the delay is higher than 128 ms, bit (tbd) of rdifdelvcg_x is set, indicating ethermap-12 is not able to compute such a differential delay, and further, bits (tbd) of rdifdelvcg_x contain invalid information. furthermore in ho vcat, when the reported differential delay is found to be greater than one configured in the rmaxdelvcg_x register, an alarm, aholoa_x, is generated (i.e., at a per vcg_x level). hol stands for head of line. note: in both cases (lo vcat and ho vcat), ethermap-12 can compute a differential delay up to 128 ms, but it can only compensate a maximum differential delay of 64 ms. - 117 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ethernet line interfaces the ethermap-12 supports two types of ethernet line interfaces: smii or gmii. the gmii ethernet line interface is used only when the ethermap-12 ethernet line side is configured for 1000 mbps operation. the smii ethernet line interface is used only when the ethermap-12 ethernet line side is configured for 10/100 mbps operation. an external signal lead, gmii/smii , provides for selection between either a single gmii ethernet line interface or up to eight independent smii ethernet line interfaces. note, that the gmii ethernet line interface uses the same leads as the smii ethernet line interface and thus these two ethernet line interfaces cannot be used simultaneously. when using the gmii interface, an external signal lead, phy/mac , selects the clock source for the output signal, gtx_clk. this allows for flexible interconnections between ethermap-12 and other common components such as ethernet phy or switch devices. figure 48 shows these various interconnection options. ethermap-12 supports up to eight independent smii interfaces. all eight smii interfaces use a common global clock and common global sync signal (smii_gclk). an external signal lead, sync_dir, controls the direction of the sync signal on the smii_gsync signal lead. the external lead phy/mac allows the 8 ethernet lines of ethermap-12 to be connected to a phy or to a mac. when phy/mac is equal to 1, ethermap-12 is connected to a phy and then is ready to accept status information from the phy. when phy/mac is equal to 0, ethermap-12 is considered to be connected to a mac and then the 8 ethernet interface need to be configured. ethermap-12 supports half duplex and full duplex for 10/100 mbps and only full duplex for 1000 mbps. in addition to the gmii/smii ethernet line interfaces, the ethermap-12 also provides support of control and status to and from external phys using a two-wire mii management interface (mdc, mdio) as per ieee 802.3u. this interface can be used with both gmii/smii interfaces. - 118 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 48. ethermap-12 to phy or switch interconnection using gmii interface gtx_clk txd tx_clk rx_clk rxd gtx_clk txd tx_clk rx_clk rxd n/c ethermap-12 phy gtx_clk txd tx_clk rx_clk rxd rx_clk rxd tx_clk txd ethermap-12 switch gtx_clk txd tx_clk rx_clk rxd rx_clk rxd tx_clk txd ethermap-12 switch n/c ethermap-12 to phy interconnection using gmii interface (i.e., mac-to-phy) gmii/smii =high phy/mac =high gmii/smii =high phy/mac =low ethermap-12 to switch interconnection using gmii interface (i.e., mac-to-mac) ethermap-12 to switch interconnection using gmii interface (i.e., mac-to-mac) gmii/smii =high phy/mac =high tx_clk is used for gtx_clk tx_clk is used for gtx_clk rx_clk is used for gtx_clk note: in gmii mode, the difference between mac-to-phy and mac-to-mac configuration is given by the different wiring, as can be seen comparing the upper and the lower two configurations in this diagram. 8 8 8 8 8 8 - 119 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ethernet mac blocks the ethermap-12 contains eight ethernet macs. however, when ethermap-12 is configured for gigabit mode, only the first mac is used for 1000 mbit/s operation. the remaining macs are disabled. when ethermap-12 is configured for 10/100 mbit/s mode, all eight macs are enabled and each can be independently configured for 10 or 100 mbit/s operation. the selection between 10/100 or 1000 mbit/s mode is done using the external signal lead gmii/smii and internal registers select between 10 or 100 mbit/s mode. in addition, if the attached phy device auto-negotiates between 10 and 100mbps, this information is passed to the mac over the smii interface and overrides any internal register setting. in the transmit direction (i.e., towards the ethernet line side), each mac can be configured to apply or not to apply padding and to append or not to append a valid fcs field to the ethernet frames. ethermap-12 supports both half duplex mode (csma/cd) and full duplex mode for 10/100 mbit/s and full duplex mode for 1000 mbit/s. pause flow control frame generation is fully configurable and supported (as per ieee 802.3x). following each ethernet frame transmission or abortion, ethermap-12 updates the appropriate transmit side rmon statistic counters. the general configuration of the macs is described in tables tbd (including selection between full or half duplex operation). furthermore table tbd specifies half duplex configuration such as: configuration of collision window, number of maximum transmission attempts following a collision before abortion, abort or transmit of an excessively deferred packet, use of alternate binary exponential back-off rule or to immediately re-transmit a packet following a collision during back pressure, use of 802.3 standard tenth collision or programmable alternate binary exponential back-off truncation. in the receive direction (i.e., from the ethernet line side), each mac scans the preamble looking for the start frame delimiter (sfd). the preamble and sfd are stripped and the remaining ethernet frame is passed on for further processing. in addition, each mac provides the capability to filter ethernet frames that have less than a configured inter-frame gap; to detect broadcast or multicast destination addresses; to check length field against the actual length of the data field portion of the ethernet frame and to check or not the fcs field of the ethernet frame. ethermap-12 supports both half duplex mode (csma/cd) and full duplex mode for 10/100 mbit/s and only full duplex mode for 1000 mbit/s. this means that the pause flow control frame detection is fully configurable and supported (as per ieee 802.3x). following each ethernet frame reception, the appropriate receive side rmon statistic counters are updated. tables tbd are used for configuration and control of the mii management interface. using the control bits of table tbd , the mdc (mii management clock) is derived from the micclk clock by applying a divide factor of 4 to 28. it is possible also to suppress or not the preamble information. in order to perform a write access, the following steps need to be followed: configure ? register address ? field (with 0x0 for control register) of table tbd , configure ? phy address ? field of table tbd , write a data value into the ? mii mgmt control ? field of table tbd , similarly, in order to perform a read access, the following steps need to be followed: configure ? register address ? field (with 0x1 for control register) of table tbd , configure ? read cycle ? field of table tbd , read a data value from the ? mii mgmt status ? field of table tbd . - 120 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ethernet half duplex in half-duplex mode of operation, two or more ethernet devices are connected to a common transmission medium and when one ethernet device transmits, the others listen. in the case where two ethernet devices transmit at once, a ? collision ? is said to have occurred. a ? jam sequence ? is transmitted by the transmitting ethernet device indicating the occurrence of a collision. the contention is resolved by each of the ethernet devices responsible for the collision, backing off, and attempting to re-transmit after a time period. this method is called carrier sense multiple access/collision detection (csma/cd). the ethermap-12 media access controller (mac) implements the 802.3 compliant csma/cd algorithm. for a complete definition of this algorithm please refer to the ieee 802.3 specification. following is an outline based on the ethermap-12 mac. note: carrier sense and collision detection status is indicated by the phy device to the ethermap-12 via the smii inter- face. please refer to the serial media independent interface (smii) specification for further details. carrier sense to begin transmission of an ethernet frame, the ethermap-12 media access controller (mac) uses three different configuration registers. after the transmission of an ethernet frame, the back-to-back inter packet gap (ipg) is enforced. after an ethernet frame is received, the non-back-to-back ipg (ipg2) is used. additionally, during the time defined by the ipgr1 configuration register, the mac monitors the carrier sense status. this carrier sense window is known as ipg1. if carrier is detected during this window, the mac does not attempt to transmit. if the carrier becomes active after the ipg1 window, transmission is begun after the proper ipg has elapsed, forcing a collision and subsequent backoff. the carrier sense window is typically configured using a two-thirds/one-third ratio, meaning that the carrier is monitored during the first two-thirds of the ipg, and is ignored during the remaining one-third. since it is not possible for the ethernet output to backpressure traffic arriving from sonet/sdh, it may be necessary to configure the ethermap-12 to more aggressively occupy the ethernet media by reducing the size of the ipg1 window. collision detection in the event the ethermap-12 mac detects a collision when the device is transmitting an ethernet frame, the mac outputs the 32-bit jam sequence. the jam sequence is made up of several bits of the crc, inverted to guarantee an invalid crc upon reception of the frame. the mac then backs off transmission of the frame (retry) based on the ? truncated binary exponential backoff ? (beb) algorithm. following this backoff time, the frame is retried. the ? no backoff ? configuration bit, when enabled, retransmits the frame without a backoff, following a collision. this option needs to be enabled with caution. alternate beb truncation the backoff time following a collision is a controlled randomization process called ? truncated binary exponential backoff ? . it is defined as an integer multiple of the slot times. the number of slot times to delay before the n th retransmission attempt is chosen as a uniformly distributed random integer r in the range: 0 r 2 k where k = min(n,10). so, after the first collision, the mac will backoff either 0 or 1 slot times. after the fifth collision, the mac will backoff between 0 and 32 slot times. after the tenth collision, the maximum number of slot times to backoff is 1024. by setting the ? alternate beb enable ? bit, the truncation point can be changed from min(n,10) to min(n,m) where m is set in the ? alternate beb truncation ? register. excessive collisions upon collision, the mac attempts re-transmission of the frame. as specified in the ieee 802.3 specification, a frame has excessive collisions if 15 re-transmission attempts have occurred. the number of retransmission attempts for excessive collisions is configurable. in the event a frame has been excessively deferred, the frame is discarded and will not be transmitted. it is possible to configure the ethermap-12 not to discard an excessively deferred frame. - 121 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 half-duplex flow control there is no ieee 802.3 compliant backpressure mechanism for half duplex. the common industry implementation is the ? raise carrier ? method. the ethermap-12 mac uses the configurable ? raise carrier ? method for flow control in half-duplex mode. in the event the ethermap-12 mac needs to backpressure the transmission medium, it raises carrier by transmitting the preamble. other devices on the transmission medium defer to the carrier. if a collision occurs due to the raised carrier, the congestion is resolved using the standardized collision-detect, backoff method. the host can not initiate flow control when raise carrier method is being used. - 122 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 flow control operation because there could be a mismatch of bandwidth rates between an ethernet port and its corresponding sonet/sdh link (i.e., transporting 100mbit/s using a single vc-3), ethermap-12 has the ability to flow control the ethernet traffic. depending on the mode of operation of the ethernet port (i.e., full duplex or half duplex), the ethermap-12 provides support for the following types of flow control mechanisms: full duplex mode (for 10/100/1000 mbit/s): when configured for full duplex mode, the pause frame (as per ieee 802.3x) is used as a flow control mechanism. half duplex mode (for 10/100 mbit/s): when configured for half duplex mode, the csma/cd algorithm is used as a back-pressure flow control mechanism. the back-pressure scheme uses the ? raise carrier ? method. table tbd provides further details on specific configuration options. for full duplex mode of operation, in the ethernet-to-sonet direction, the ethermap-12 provides support for pause frame flow control when ? transmit flow control enable ? and ? receive flow control enable ? control bits are set in table tbd and the ctfcmodex register is configured appropriately. in the case of 10/100 mbit/s, the ethermap-12 allocates eight separate buffers (i.e., txfifos), on a per ethernet port basis, within the external sdram. in the case of 1000 mbit/s, the ethermap-12 allocates a single buffer (i.e., the previous eight separate buffers are concatenated into a single contiguous buffer) for the single ethernet port within the external sdram. the txfifos buffer/rate adapt incoming traffic from the ethernet ports before they are transmitted onto sonet/sdh. so, when there is a mismatch of bandwidth rates between the ethernet ports and the sonet/sdh link, a situation can occur where the txfifo fill level will begin to increase and eventually lead to an overflow condition. ethermap-12 employs a mechanism of high (rhwtmk_msb_x, rhwtmk_lsb_x) and low (rlwtmk_msb_x, rlwtmk_lsb_x) watermarks per txfifo. associated with each of these watermarks is a configurable pause frame timer value (i.e., high watermark corresponds to rhwpt_x register and low watermark corresponds to rlwpt_x register). lastly, the rhipse_x register is used to configure the point in time when the fill level of the txfifo is checked in order to determine transmission of further pause frames. when the fill level of the txfifo exceeds the high watermark (i.e., rhwtmk_msb_x, rhwtmk_lsb_x), the corresponding transmit mac is requested to generate a pause flow control frame (with a pause timer value as per the rhwpt_x register) towards the ethernet line side. once the pause frame is transmitted, the value of the rhwpt_x register is loaded into an internal pause timer (i.e., a separate internal pause timer exists per txfifo). this internal pause timer starts to decrement at the rate of the corresponding mac. as the internal pause timer decrements, when its count value is equal to that of the rhipse_x register, at this point the fill level of the txfifo is checked and the following possible actions can be taken: if the txfifo fill level is equal to or above the high watermark, the corresponding transmit mac will be requested to generate a pause flow control frame using the pause timer value from the rhwpt_x register. at this time, the internal pause timer is re-loaded again with the contents of the rhwpt_x register and begins again to decrement at the rate of the corresponding transmit mac. if the txfifo fill level is below the high watermark but above the low watermark, the corresponding transmit mac will not request to generate a pause flow control frame and the internal pause timer is reset to zero. if the txfifo fill level is below the low watermark, the corresponding transmit mac will generate a pause flow control frame using the pause timer value from the rlwpt_x register. note when a pause frame must be sent to the ethernet client (sonet to ethernet direction), if there a frame in the tx fifo that has just been started, the transmission of this frame is completed, and the pause frame follows immediately. in other words, the tx fifo cannot be preempted. while the internal pause timer is decrementing and is not equal to zero, if a txfifo overflow condition occurs, an alarm atxfifox is asserted, further writes into the txfifo are stopped and the last/most recent ethernet frame found to be incomplete is discarded. any follow-on ethernet frames, from the ethernet line side, are - 123 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 discarded and counted using the rpcl2tdropovfx counter. during this condition, the contents of the txfifo continue to be read out and transmitted onto sonet/sdh as the fill level starts to recede. no idle frames are sent to sonet/sdh side other than those required minimally as per the configured encapsulation protocol. the corresponding transmit mac makes a request to generate a pause flow control frame (using the contents of the rhwpt_x register) and the internal pause timer begins to decrement (after being loaded with the contents of rhwpt_x register) in order to determine when to check the txfifo fill level. when checking the txfifo fill level, the following possible actions can be taken: if the txfifo fill level is still equal to or above the high watermark, then further writes into the txfifo remain suspended and the procedure outlined above is followed. if the txfifo fill level is below the high watermark, then further writes into the txfifo are allowed to begin and the procedure outlined above is followed. for half duplex mode of operation, in the ethernet-to-sonet direction, the ethermap-12 provides the common back-pressure flow control mechanism in order to manage the txfifo fill levels. if the txfifo fill level is equal to or above the high watermark, the corresponding transmit mac will be requested to apply/enable the back-pressure mechanism (by raising carrier). this is also the case when an overflow condition is detected using the alarm, atxfifox. on the other hand, if the txfifo fill level is below the low watermark, the corresponding transmit mac will not apply/enable the back-pressure mechanism. in the sonet-to-ethernet direction, the ethermap-12 provides the ability to configure handling of pause flow control frames that may be received from the sonet/sdh side. using the crfcmodex register, a selection can be made to pass through or discard the received pause flow control frames, that are to be transmitted to the ethernet line side. in any event, all received pause flow control frames are counted (per ethernet port) using the rpcrpausex counter. when changing flow control parameters from their default values, the following procedure should be followed: from a hardware reset: 1. configure the flow control parameters (tables tbd and tbd). 2. de-assert the mac soft reset (see table tbd - reset tx, reset rx). 3. enable the transmit and receive mac blocks (see table tbd - transmit enable and receive enable). from an already configured device: 1. disable the transmit and receive mac blocks. 2. assert the mac soft reset. 3. configure the flow control parameters (tables tbd and tbd). 4. de-assert the mac soft reset. 5. enable the transmit and receive mac blocks. - 124 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 encapsulation / decapsulation when the ethernet line side is configured for smii interface, the ethermap-12 device provides support for up to eight independent 10/100 mbit/s ethernet mac blocks. each 10/100 mbit/s ethernet mac block is further allocated to a dedicated protocol encapsulation/decapsulation block (up to eight independent blocks) for servicing its bi-directional ethernet frame traffic. when the ethernet line side is configured for gmii interface, the ethermap-12 device provides support for a single 1000 mbit/s ethernet mac block (shared with the first 10/100 mbit/s ethernet mac block). the 1000 mbit/s ethernet mac block is allocated to a dedicated protocol encapsulation/decapsulation block (the first block is shared between 10/100 mbit/s and 1000 mbit/s) for servicing its bi-directional ethernet frame traffic. each protocol encapsulation/decapsulation block can be independently configured to use one of the following protocols for transport of ethernet mac frames over a sonet/sdh link: generic framing procedure (gfp), link access procedure - sdh (laps), link access procedure frame mode (lapf), point-to-point protocol (ppp) with bridging control protocol (bcp) and transparent hdlc. by default, the protocol encapsulation blocks are configured for laps and the protocol decapsulation blocks are configured for byte-synchronous hdlc (i.e., laps mode). the procedure for changing the configuration of the encapsulation mode of the mac is as follows; 1) place all the vt corresponding to the mac in ais; 2) perform a soft reset per channel by setting the tx_resetsx register to 0x91; 3) change the configuration of the corresponding mac; 4) clear the soft reset per channel by writing 0x00 in tx_resetsx; 5) remove the ais indication for all the vt corresponding to the mac. in the case of gfp linear frame mode, changing the configuration of the encapsulation mode of the mac is as follows; 1) place all the vt corresponding to the vcg (assigned to several mac) in ais (see note 1 below); 2) perform a soft reset per channel by setting the tx_resetsx register to 0x91 to all the mac involved in the vcg; 3) change the configuration of the corresponding macs; 4) clear the soft reset per channel by writing 0x00 in tx_resetsx; 5) remove the ais indication for all the vt corresponding to the vcg. the procedure for changing the configuration of the decapsulation mode of one vcg is as follows; 1) perform a soft reset of the mac corresponding to the vcg by setting to 1 the reset tx function (bit tbd) (in the address tbd for the corresponding mac); 2) perform a soft reset per channel by setting the rx_resetsx register to 0x91; 3) change the configuration of the corresponding vcg; 4) clear the soft reset of the mac by clearing the reset tx function (bit tbd) (in the address tbd for the corresponding mac); 5) clear the soft reset per channel by writing 0x00 in rx_resetsx; 6) enable the mac corresponding to the vcg. in the case of gfp linear frame mode, changing the configuration of the decapsulation mode of one vcg is as follows; 1) perform a soft reset of all the mac corresponding to the vcg by setting to 1 the reset tx function (bit tbd) (in the address tbd for these macs); 2) perform a soft reset per channel by setting the rx_resetsx register to 0x91 for all the corresponding mac; 3) change the configuration of the corresponding vcg; 4) clear the soft reset of the mac by clearing the reset tx function (bit tbd) (in the address tbd for the corresponding macs); 5) clear the soft reset per channel by writing 0x00 in rx_resetsx for all the corresponding mac; 6) enable all the mac corresponding to the vcg. - 125 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 gfp generic framing procedure (gfp) is a protocol for mapping packet data into an octet-synchronous transport such as sonet/sdh. unlike hdlc-based protocols, gfp does not use any special characters for frame delineation. instead, it uses a cell delineation protocol, such as used by atm, to encapsulate variable length packets. a fixed amount of overhead is required by the gfp encapsulation that is independent of the contents of the packet size. the gfp protocol is specified in the itu-t g.7041/y.1303 standard. figure 49 shows the format of a gfp frame with a ethernet mac frame payload (denoted by the shaded area) relationship. figure 49. format of gfp frame with an ethernet mac frame payload as shown in figure 49 , the gfp overhead can consist of two headers: a core header, which consists of a two byte payload length indicator (pli) field and a two byte core header error control (chec) field. the core header is used for frame delineation. a payload header, which consists of a type header and an extension header (optional). the type header consists of a two byte type field and a two byte type header error control (thec) field. the type header is used to indicate the format and content of the payload information field. the ethermap-12 device supports frame based mapping for ethernet mac frames only. the extension header used for managing logical links, classes of service and source/destination addresses. two forms of extension headers are supported: null extension header and linear extension header. for null extension header support, no additional extension header bytes are required (as per itu-t g.7041/y.1303). for linear extension header support, four bytes are required in addition to the type header. these consist of a one byte channel id (cid) field, a one byte spare (reserved) field and a two byte extension header error control (ehec) field. ethernet mac frame gfp frame o ctets 2 pli field 2 chec field octets 2 type field 7 p reamble 2 thec field 1 start of frame delimiter 0-60 extension header 6 destination address (da) 6 source address (sa) 2 l ength/type g fp mac client data payload information field p ad 4 frame check sequence (fcs) bits 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 - 126 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 as shown in figure 49 , the gfp payload information field is used to carry a complete ethernet mac frame. further, an optional payload fcs field (4 bytes) may be inserted after the gfp payload information field. the optional payload fcs field contains a 32-bit crc sequence that protects the contents of the gfp payload information field only. in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for gfp, the following functions are supported: encapsulate ethernet mac frame within a gfp frame. each ethernet mac frame is encapsulated with a core header, a payload header and an optional payload fcs field. for the core header, the pli and the chec fields are generated. for the type header within payload header, the pti, pfi, exi, upi and thec fields are generated and configurable. for the extension header (when in linear frame mode) within payload header, the cid, spare and ehec fields are generated and configurable. cptix(2-0) gfp payload type identifier field configuration 0x0 - 0x7 indicates contents of the pti field for gfp client data frames only. (default = 0x0) cpfix bit tbd gfp payload fcs indicator control 0 the pfi bit within the gfp payload header is set to zero (0). gfp payload fcs field is not inserted. (default) 1 the pfi bit within the gfp payload header is set to one (1). gfp payload fcs field is inserted. cexix(3-0) gfp extension header identifier field configuration 0x0 - 0xf indicates contents of the exi field with in the gfp payload header. (default = 0x0) cupix(7-0) gfp user payload identifier field configuration 0x00 - 0xff indicates contents of the upi field for gfp client data frames only. (default = 0x01) csparex (7-0) gfp spare field configuration 0x00 - 0xff indicates contents of the spare field within the gfp extension header when using gfp linear frame structure. (default = 0x00) cfecidx (7-0) gfp channel id (cid) field configuration 0x00 - 0xff indicates contents of the cid field within the gfp extension header when using gfp linear frame structure. (default = 0x00) - 127 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 gfp core header scrambling can be enabled/disabled using the ctcscrx register. gfp client data and client management frame formats are supported. gfp idle frame generation and insertion is supported. self-synchronous scrambler (x 43 +1 polynomial) for the payload header, payload information field and payload fcs field (optional) can be enabled/disabled according using the ctpscrdx register. furthermore, the scrambler can be initialized to a default state using the ctscrinitx register. 32-bit crc sequence generation for the payload fcs field (optional), over all octets of the gfp payload information field only, is supported. gfp frame multiplexing (when in linear frame mode, cexix=1) from multiple ethernet ports using a configurable scheduling algorithm is supported. for further details, please see the following section ? gfp linear frame mode operation ? on page 134 . detection and handling of errored ethernet mac frames on gfp ingress is supported. an alarm, atetherrx, is generated when an errored ethernet mac frame is detected and discarded for the transmit direction. generation of gfp client signal fail (csf) indication is supported using the ctgfptxcsfx register. the ctgfptxcsfx allows to enter into the csf mode (when set to 1). in that mode, every 100 ms, a csf indication is transmitted to the line. the atgfpcsfx alarm indicates the activation of this mode. to exit from this mode, the ctgfptxcsfx must be cleared. ctcscrx bit tbd gfp core header scrambling control 0 enable scrambling of gfp core header only. (default) 1 disable scrambling of gfp core header only. ctpscrdx bit tbd gfp payload area scrambling control 0 enable scrambling of gfp payload area only. (default) 1 disable scrambling of gfp payload area only. ctscrinitx bit tbd gfp payload scrambler initialization control 0 scrambler is initialized with an all zeros state. (default) 1 scrambler is initialized with an all ones state. ctgfptxcsfx bit tbd gfp csf frame transmit control 0 disable gfp csf frame transmit mode. (default) 1 enable gfp csf frame transmit mode. beginning at the next gfp frame, a csf indication is transmit every 100 ms period (i.e., no gfp client data frames can be transmitted). gfp idle frames are transmitted in the interim. - 128 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to insert errors in chec, thec and ehec fields for testing is configurable respectively using the ctchecerrx, ctthecerrx and ctehecerrx registers (self-clearing type, i.e., error is inserted only in a single frame). furthermore, the chec generator can be initialized to a default state using the cthecinitialx register. for each gfp frame byte that is input to the chec/thec/ehec generator, the bit-order within the byte can be swapped/reversed using the cthecswapinx register. for each gfp chec/thec/ehec byte from the chec/thec/ehec generator, the bit-order within the chec/thec/ehec byte can be swapped/reversed using the cthecswapoutx register before transmission to sonet/sdh. this does not affect the chec/thec/ehec calculation result but rather the transmission bit-order of each fcs byte into sonet/sdh. ctchecerrx bit tbd gfp chec error insertion 0 disable chec error insertion. (default) 1 enable chec error insertion. error is inserted by inverting the calculated chec field before transmission. ctthecerrx bit tbd gfp thec error insertion 0 disable thec error insertion. (default) 1 enable thec error insertion. error is inserted by inverting the calculated thec field before transmission. ctehecerrx bit tbd gfp ehec error insertion 0 disable ehec error insertion. (default) 1 enable ehec error insertion. error is inserted by inverting the calculated ehec field before transmission. cthecinitialx bit tbd gfp chec generator initialization control 0 chec generator is initialized with an all zeros state. (default) 1 chec generator is initialized with an all ones state. cthecswapinx bit tbd gfp chec/thec/ehec input swap control 0 for each gfp frame byte at the input of the chec/thec/ehec generator, the bit-order is preserved (i.e., not swapped/reversed). (default). 1 for each gfp frame byte at the input of the chec/thec/ehec generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). - 129 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to force abort generation is configurable using the ctabtgx register. detection of fifo overflow/underflow conditions and size (maximum) of gfp payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atgfpfmerrx alarm. the limit of the gfp payload information size is programmable using the register rtmaxflx. the default value is 0x600. an alarm, atgfpmaxerx, is generated when the size of the gfp payload information exceeds the value configured in rtmaxflx register. ability to insert gfp client management/control frames by the host is supported. a 128-byte buffer (using 128 rtctl_x(8-0) registers) per mac is provided to store a single gfp client management/control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits tbd) is part of the gfp client management/control frame. the host must write a valid formatted (including overhead bytes) gfp client management/control frame into the buffer such that only additional processing steps performed are: core header scrambling and payload area scrambling (note: if payload fcs is required then this is provided by the host). the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a gfp client management/control frame. step 2: once the gfp client management/control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the gfp client management/control frame is ready for transmission. step 3: during the next gfp inter-frame window (i.e., after completion of the gfp frame currently being transmitted), the stored gfp client management/control frame is inserted into the datapath for transmission to sonet/sdh. step 4: once the gfp client management/control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-12 and an alarm, atctlx, is generated. the alarm cthecswapoutx bit tbd gfp chec/thec/ehec output swap control 0 for each gfp chec/thec/ehec byte that are output from the chec/thec/ehec generator, the bit-order is preserved (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each gfp chec/thec/ehec byte that are output from the chec/thec/ehec generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being trans- mit to sonet/sdh. ctmaxflx (15-0) gfp payload information field size 0x0001 - 0x2800 indicates maximum number of octets in the gfp payload information field that is transmitted. (default = 0x2800). when cpfix=1, for a gfp payload length that exceeds the configured value in the ctmaxflx register, the payload fcs is inverted before transmission to sonet/sdh. this will ensure that the terminating end discards the gfp frame. when cpfix=0, for a gfp payload length that exceeds the configured value in the ctmaxflx register, the current gfp payload is padded with 0xff octets up to the configured length. - 130 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 can be used to provide an indication of the next available gfp client management/control frame transmission. ability to filter mapping of select gfp frames for transmission to sonet/sdh is provided using ctgfppdux register. transmission of all gfp client management/control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of gfp frames (i.e., including gfp client management/control frames) for transmission to sonet/sdh. maintains transmit statistics counters. two types of counters are provided: the total number of gfp frame payloads transmitted (rpctgfpframex register) and the total number of gfp frame payload octets transmitted (rpctgfpbytex register). these are also described in ta b l e t b d . in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for gfp, the follow- ing functions are supported: stctlbx bit tbd gfp client management/control frame buffer status indication 0 buffer is empty and is able to receive a new gfp client management/control frame. (default) 1 buffer is full and is not able to receive a new gfp client management/control frame. ctctlbrstx bit tbd gfp client management/control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. ctgfppdux bit tbd selective gfp frame mapping filter control 0 gfp frames are allowed to pass for mapping into sonet/sdh. (default) 1 gfp frames are not allowed (i.e., frames are discarded) to pass for map- ping into sonet/sdh. ctoffx bit tbd generic gfp frame mapping filter control 0 all types of gfp frames (i.e., including gfp client management/control frames) are allowed to pass for mapping into sonet/sdh. (default)) 1 all types of gfp frames (i.e., including gfp client management/control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only gfp idle frames are mapped into sonet/sdh. - 131 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 decapsulate to extract the ethernet mac frame from within a gfp frame after frame delineation and sync is achieved. robustness of gfp frame delineation acquisition using four virtual framers is configurable using the crdeltax register. processing of null or linear header types is configurable using the crgfphdrx register. core header descrambling can be enabled/disabled using the crcdscrx register. single-bit error detection and correction in the core header, type header and extension header is configurable. multiple-bit error detection in the core header, type header and extension header is supported and these frames are discarded. crdeltax (2-0) gfp re-synchronization control 0x0 - 0x7 indicates values of delta to be used in the gfp delineation process. (default = 0x1) crgfphdrx bit tbd gfp header type processing control 0 only gfp null header type is processed. gfp frames received with other types of headers are discarded. (default) 1 only gfp linear header type is processed. gfp frames received with other types of headers are discarded. crcdscrx bit tbd gfp core header de-scrambling control 0 enable de-scrambling of gfp core header only. (default) 1 disable de-scrambling of gfp core header only. crcordisx bit tbd gfp core header single-bit error correction control 0 for gfp core header, enable single-bit error correction and all received gfp frames detected with single-bit errors are corrected and passed. (default) 1 for gfp core header, disable single-bit error correction and all received gfp frames detected with single-bit errors are discarded. crthecsx bit tbd gfp type header single-bit error correction control 0 for gfp type header, enable single-bit error correction and all received gfp frames detected with single-bit errors are corrected and passed. (default) 1 for gfp type header, disable single-bit error correction and all received gfp frames detected with single-bit errors are discarded. - 132 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 gfp client data and client management frame formats are supported. gfp idle frame detection and discard is supported. self-synchronous descrambler (x 43 +1 polynomial) for the payload header, payload information field and payload fcs field (optional) can be enabled/disabled using the crpscrdx register. 32-bit crc sequence generation and checking for the payload fcs field (optional), over all octets of the gfp payload information field only, is supported. an option is provided to pass or discard gfp frames with a fcs error using the crgfpfcserx register. gfp frame demultiplexing (when in linear frame mode) to multiple ethernet ports based on configurable cid fields is supported. for further details, please see the following section ? gfp linear frame mode operation ? on page 134 . detection of gfp client signal fail (csf) indication is supported. detection of size (maximum) of gfp payload information field via alarm and interrupt generation. the max- imum size of the received gfp frame payload information field (in octets) can be configured using the rrmaxflx register. an alarm, argfpmaxerx, is generated when the size of the received gfp frame pay- load information field (in octets) exceeds the value configured in rrmaxflx register. crehecsx bit tbd gfp extension header single-bit error correction control 0 for gfp extension header, enable single-bit error correction and all received gfp frames detected with single-bit errors are corrected and passed. (default) 1 for gfp extension header, disable single-bit error correction and all received gfp frames detected with single-bit errors are discarded. crpscrdx bit tbd gfp payload area de-scrambling control 0 enable de-scrambling of gfp payload area only. (default) 1 disable de-scrambling of gfp payload area only. crgfpfcserx bit tbd gfp fcs check handling 0 received gfp frames detected with a payload fcs error (when fcs is present) are discarded. (default) 1 received gfp frames detected with a payload fcs error (when fcs is present) are not discarded. gfp: host insertion/extraction of management/control frames crmaxflx (15-0) gfp payload information field size 0x0001 - 0x2800 indicates maximum number of octets in a received gfp frame payload information field not including the payload header and fcs bytes. (default = 0x2800) - 133 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 gfp host extraction of management/control frames ability to filter and extract gfp client management/control frames by the host is supported. a 520-byte buffer (using 520 rrlmix_ (8-0) registers) per mac is provided to store multiple gfp client manage- ment/control frame for the host extraction. lmi is an acronym for local management interface. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the gfp client management/control frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and including the byte with msb = 0 are not a part of the received frame. the host is provided with a gfp client management/control frame such that only the following processing have been performed: gfp frame delineation, core header descrambling and payload area descrambling. a reset of the buffer can be generated using the crctlbrstx register. this reset will clear the srctlavx status register and causes the 520 byte buffer to clear its present contents. the rrgfpcpx register is used to configure the payload header type field value to be checked in order to extract the gfp client management/control frame and the rrctlmaska1x register is used as a bit level mask that is applied to the crgfpcpx register. below is an example of how the host can use this buffer: step 1: if the buffer is empty, srctlavx=0 and the host is not allowed to read for a new gfp client management/control frame. step 2: once the gfp client management/control frame has been received, the srctlavx status register is set (srctlavx=1) by the ethermap-12 to indicate that at least one gfp client management/control frame is ready for extraction by the host. further management/control frames may be written into the buffer if received. if so, the srctlavx bit will become set again. an alarm is provided (arctlovf) to indicate the overflow of the 520-byte buffer. srctlavx bit tbd gfp client management/control frame buffer status indication 0 buffer is empty and no complete gfp client management/control frame has been received/stored. (default) 1 buffer is full with at least one complete gfp client management/control frame received. crctlbrstx bit tbd gfp client management/control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. rrgfpcpx(15-0) gfp client management/control frame payload header type field contents 0x0000 - 0xffff indicates contents of the gfp client management/control frame payload header type field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaska1 mask register. (default = 0x8000) the structure of this register is as follows: pti field value = bits (15-13), pfi field value = bit 12, exi field value = bits (11-8) and upi field value = bits (7-0). - 134 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to filter decapsulation of select gfp frames that are received from sonet/sdh is provided using crgfppdux register. reception of all gfp client management/control frames (i.e., control frames des- tined for extraction by host) are not affected by this register. maintains receive statistics counters. all gfp receive side statistic counters are described in ta b l e t b d . gfp linear frame mode operation this mode allows support for scenarios where traffic from multiple independent mac ports can be transported within a single vcg on sonet/sdh. the use of this mode requires configuration for linear frame extension header (which is added to the transported gfp frame) and of the cid tables (which configure the ethermap-12 for this operation). note that, for each vcg operating in gfp linear frame mode, the extension header field (exi) within the gfp payload header must be configured using the cexi register for the transmit side. on the receive side, the crgfphdrx register must be configured to allow for correct processing of gfp linear frames. transmit side linear extension header the following registers are used for configuration inputs for the transmit side linear extension header bytes. these bytes are written in during system configuration, and are updated only in a static manner by host processor. spare field: for each mac port, the csparex register is used to configure the insertion value of the spare field within the linear frame extension header. channel id field (cid): for each mac port, the cfecidx register is used to configure the value of the cid field. this field will be common to all the frames transmitted from that mac port; thus the contents of the cfecidx register will represent the originating mac port id, when the frame is received by the far-end mac port. transmit side cid configuration tables when a vcg operates in gfp linear mode, several mac ports may be configured to be multiplexed into it. for any vcg, the cidtablex_0, cidtablex_1, cidtablex_2, cidtablex_3, cidtablex_4, cidtablex_5, cidtablex_6, cidtablex_7 registers will allow configuration of specific mac ports that will be multiplexed in that vcg. these registers are only modified in a static manner by the host upon initialization of the gfp link. note that the 8 mac ports need not be all involved in the frame multiplexing process: for example, only a rrctlmaska1x(15-0) gfp client management/control frame payload header type field contents mask 0x0000 - 0xffff mask value that is applied to the rrgfpcpx register contents to aid in the fil- tering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrgfpcpx register is used for filtering. (default = 0xffff) crgfppdux bit tbd selective gfp frame decapsulation filter control 0 all gfp frame types received frames from sonet/sdh are allowed to be decapsulated. 1 only gfp csf and gfp client management/control frames matching the rrgfpcpx register are allowed to be decapsulated. (default) - 135 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 subset of the ? n ? ethernet ports may be multiplexed in a given vcg. the operation of the cidtablex registers can be represented with a example scheduling matrix, shown in table 3 . this matrix is used to configure/control the multiplexing process for all the participating mac ports configured for gfp linear frame mode. table 3 shows an example configuration of the scheduling matrix. the vcg are represented along the vertical axis; on horizontal axis, the matrix represents the mac ports that a vcg will service. table 3: scheduling matrix scheduling matrix explanation: 1) the above matrix can be interpreted as follows: transport path vcg0 (represented on the top row), will first transmit one frame from mac1, then one frame from mac3, then one frame from mac1, then one frame from mac2, then one frame from mac2, then one frame from mac3, then one frame from mac1, then one frame from mac1 etc. this cycle is continuously repeated. for transport path vcg 1, the mac ports are serviced in this order: 7, 4, 7, 7, 4, 7, 4, 7, 7, 4, etc. for transport path vcg 2, there are no participating mac ports. for transport path vcg 3, there are no participating mac ports. for transport path vcg 4, there are no participating mac ports. for transport path vcg 5, there are no participating mac ports. for transport path vcg 6, there are no participating mac ports. for transport path vcg 7, the mac ports are serviced in this order: 5, 5, 5, 0, 0, 5, 0, 5, etc. 2) for each vcg row, each entry identifies the mac port (configured for gfp linear frame) to be serviced. also, each entry represents only one complete ethernet frame to be accepted each time into the multiplexing process. 3) ? n ? represents a null value. the entries are read/serviced from left to right and wrap around to beginning of the cycle after servicing the last entry (i.e., entry number 7). a null value is used to terminate the servicing sequence order back to the first entry in the row (i.e., entry number 1). on initialization/power-up, all entries in the matrix are configured to a null value. 4) a null value cannot exist in the middle of the servicing sequence order (i.e., for example to be used to skip a service cycle). it is only allowed at the end of the servicing sequence order (see 2 above). 5) a mac port is not used across/in multiple vcgs. however, within a single vcg, an ethernet port is allowed multiple entries. vcg013122311 vcg1747747nn vcg2nnnnnnnn vcg3nnnnnnnn vcg4nnnnnnnn vcg5nnnnnnnn vcg6nnnnnnnn vcg755500505 - 136 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 6) only mac ports configured for gfp linear frame mode are allowed to participate in the scheduling matrix multiplexing process. 7) ethernet port 3 is participating in the vcg 0 multiplexing process, this means that vcg 3 is only allowed to use other ethernet ports if they are configured for gfp linear frame mode. no laps, lapf or gfp null encapsulated ethernet frames are allowed in vcg 3. 8) when operating in gfp linear frame mode, the core header scrambling is performed by each of the separate mac blocks before the gfp linear frame is sent to the scheduling matrix for multiplexing. 9) when operating in gfp linear frame mode, the payload scrambling is only performed after the gfp linear frames have been multiplexed (as per the scheduling matrix) for each vcg separately. 10) table 4 shows how the matrix is mapped in the ethermap-12 register memory map. table 4: scheduling matrix mapped in the ethermap-12 register map each register cidtablex_n comprises of four bits: the most significant bit, cidtablex_n [3], indicates "entry active" (when set to '1') or "entry not active" (when set to '0'). the remaining least significant bits, cidtablex_n [2-0], indicate the select mac port. receive side linear extension header the crgfphdrx register is used to configure the type of gfp payload header (i.e., null or linear) processing for the gfp receive side. for the receive direction, the clecidx register is used to assign/configure a unique local-end cid number to each receive side mac port. this is used for processing a match condition between the local-end cid number and the cid field of the received gfp linear frame. receive side cid configuration tables for every vcg, operating in gfp linear frame mode, being received from sonet/sdh side, there is a receive cid table using crgfpcidxi (where x = 0 - 7 gfp decapsulation blocks and i = 0 - 7 entries of the x = 0 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 1 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 2 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 3 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 4 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 5 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 6 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 7 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 clecidx (7-0) gfp local-end cid value configuration 0x00 - 0xff indicates a unique local-end cid number assigned to a local receive ethernet port. (default = 0x00) - 137 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 receive cid table) registers. each table can be configured with up to eight cid values, corresponding to a maximum of eight ethernet ports. this enables a filtering function to be made on the received gfp frames by comparing their cid field values with the table of expected cid values. example: if vcg0 receives a frame, the cid field is compared against all the cid values listed in crgfpcid01, crgfpcid02, crgfpcid03, crgfpcid04, crgfpcid05, crgfpcid06 and crgfpcid07 registers. after this check, one of the following will happen: i) if cid value of the received frame matches any of cid values in the list, the frame is passed through, the ethernet frame is decapsulated and forwarded to the local receive ethernet port with the matching local-end cid number. ii) for all received gfp linear frames with matching cid values, when a far end receive csf indication is detected for a select cid value, an alarm, argfpfecsfcidxi (where x = 0 - 7 vcg decapsulation blocks; i = 0 - 7 entries of the receive cid table), is generated for that cid value. iii) when a match is not detected with the received gfp linear frame, the gfp frame is discarded and an alarm is generated. an alarm, argfpciderrx (where x = 0 - 7), is generated when the received gfp linear frame contains an unsupported cid value (i.e., a mismatch condition against the local end cid numbers). note that the order of the cid in the receive cid table is not important and that a cid number entry can only exist in once in the receive cid table for one given vcg (i.e., cannot have the same cid number entry exist in multiple tables). this check is performed by the software driver. - 138 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 laps laps is a hdlc-like framing structure to encapsulate ieee 802.3 ethernet mac frame to provide a point-to- point full duplex simultaneous bidirectional operation. the laps protocol is specified in the following standards: itu-t x.85/y.1321 and itu-t x.86. figure 50 shows the format of a laps frame with a ethernet mac frame payload (denoted by the shaded area). figure 50. format of laps frame with an ethernet mac frame payload in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for laps, the following functions are supported: encapsulate ethernet mac frame within a laps frame. each ethernet mac frame is encapsulated with a start flag (0x7e), address, control and sapi fields, a 32-bit fcs field, and a closing flag (0x7e). field insertions except the start flag can be disabled through configuration. when field insertion is enabled, the contents of the address, control and sapi fields are configurable. msb flag (0x7e) lsb 1 octet msb address (0x04) lsb 1 octet msb control (0x03) lsb 1 octet msb first octet of sapi (0xfe) lsb 1 octet msb second octet of sapi (0x01) lsb 1 octet destination address (da) 6 octets source address (sa) 6 octets length / type 2 octets mac client data 46 - 10000 octets pa d fcs of mac 4 octets fcs of laps 4 octets msb flag (0x7e) lsb 1 octet msb bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb - 139 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the management of the address and control field is performed according to the ctacselx register. the management of the sapi field is controlled by the ctsapix register. shared flag (start and closing) generation is configurable. idle flag generation and insertion is supported. the ctflagx register allows to configure the minimum number of flags to be inserted between two consecutive laps frames. self-synchronous scrambler (x 43 +1 polynomial) can be enabled or disabled. the ctscrdx register allows to enable/disable scrambling of laps frame. furthermore, the scrambler can be initialized to a default state using the ctscrinitx register. ctacselx bit tbd ctacselx bit tbd laps address and control field insertion management 0 0 address and control field contents set to all zeros. 0 1 address and control field contents contain fixed default values (i.e., address=0x04, control=0x03). (default). 10reserved. 1 1 address and control field contents are taken from the rtacfdx register. ctsapix bit tbd laps sapi field insertion management 0 sapi field contents are taken from the rtsapfdx register. 1 sapi field contents set to all zeros. ctflagx bit tbd laps flag insertion 0 a single flag are inserted between sequential laps frames (i.e., a shared flag). 1 minimum of two flags are inserted between two consecutive laps frames. (default). ctscrdx bit tbd laps scrambling control 0 enable scrambling of laps frame. (default) 1 disable scrambling of laps frame. ctscrinitx bit tbd laps scrambler initialization control 0 scrambler is initialized with an all zeros state. (default) 1 scrambler is initialized with an all ones state. - 140 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 32-bit fcs generation over all bits of the address, control, sapi, payload information field (shaded area as shown in figure 50 ) not including any flags and abort sequences, is configurable using the ctfcsx register. furthermore, the fcs generator can be initialized to a default state using the ctfcsinitiallx register. for each laps fcs byte from the fcs generator, the bit-order within the fcs byte can be swapped/reversed using the ctfcsswapoutx register before transmission to sonet/sdh. this does not affect the fcs calculation result but rather the transmission bit-order of each fcs byte into sonet/sdh. for each laps frame byte that is output from the fcs generator, the bit-order within the byte can be swapped/reversed using the ctfcsswapoutx register before it is transmitted to sonet/sdh. transparency processing (octet stuffing for flags and control escape) is supported. byte stuffing occurs between start and closing flags. stuffing replaces each byte within a laps frame that matches the flag or control escape code bytes with a two-byte sequence. ctfcsx bit tbd laps fcs generation/calculation mode 0 32-bit fcs calculation is disabled and all four fcs field octets are not inserted. 1 32-bit fcs calculation is enabled and all four fcs field octets are inserted. (default) ctfcsinitiallx bit tbd laps fcs generator initialization control 0 fcs generator is initialized with an all zeros state. 1 fcs generator is initialized with an all ones state. (default) ctfcsswapinx bit tbd laps fcs input swap control 0 for each laps frame byte at the input of the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed). in this case, the least significant bit of each byte is input first into the fcs generator. (default). 1 for each laps frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). in this case, the most significant bit of each byte is input first into the fcs generator. ctfcsswapoutx bit tbd laps fcs output swap control 0 for each laps fcs byte output from the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each laps fcs byte output from the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being transmit to sonet/sdh. - 141 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to insert fcs errors for testing is configurable using a self-clearing ctfcsex register (i.e., error is inserted only in a single frame). ability to force abort generation is configurable. the ctabtgx register allows to force (ctabtgx=1) the abortion of the current encapsulated frame by sending 0x7d and 0x7e bytes. detection of fifo overflow/underflow conditions and size (maximum) of laps payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atlpferrx alarm. the limit of the laps payload information size (in octets) is programmable using the rtmaxflx(15-0) register. an alarm, atmaxerx, is generated when the size of the laps payload information field exceeds the value configured in rtmaxflx register. ability to insert laps control frames by the host is supported. a 128-byte buffer (using 128 rtctl_x(8-0) registers) per mac is provided to store a single laps control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the laps control frame. the host must write a valid formatted (including overhead bytes) laps control frame into the buffer such that only additional processing steps performed are: fcs calculation, byte stuffing, addition of flags and scrambling. the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a laps control frame. step 2: once the laps control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the laps control frame is ready for transmission. step 3: during the next laps inter-frame window (i.e., after the closing flag of the preceding laps frame and before the opening flag of the following laps frame), the stored laps control frame is inserted into the datapath for transmission to sonet/sdh. step 4: once the laps control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-12 and an alarm, atctlx, is generated. the alarm can be used to provide an indication of the next available laps control frame transmission. ctfcsex bit tbd laps fcs error insertion 0 the 32-bit fcs is transmitted without any error insertion. (default) 1 the 32-bit fcs is errored (i.e., inverted) before transmission. ctabtgx bit tbd laps transmit abort generation 0 no abort generated. (default) 1 current frame under transmission is aborted by 0x7d followed by 0x7e. rtmaxflx (15-0) laps payload information field size 0x0000 - 0x2800 indicates maximum number of octets in the laps payload information field that is transmitted. (default = 0x2800) stctlbx bit tbd laps control frame buffer status indication 0 buffer is empty and is able to receive a new laps control frame. (default) - 142 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to filter mapping of laps frames for transmission to sonet/sdh is provided using ctlppdux register. transmission of all laps control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of laps frames (i.e., including laps control frames) for transmission to sonet/sdh. maintains transmit statistics counters. two types of counters are provided: the total number of laps frame payloads transmitted (rpctlapsframex register) and the total number of laps frame payload octets transmitted (rpctlapsbytex register) to sonet/sdh. these are also described in ta b l e t b d . in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for laps, the following functions are supported: decapsulate to extract the ethernet mac frame from within a laps frame. field extraction and checking, except the start and closing flags, can be disabled through configuration. when field extraction and checking is enabled, the contents of the address, control and sapi fields of a received laps frame are validated against configurable stored values. further, an option to discard frames with a mismatch of one of the fields, is configurable. the cracselx(1:0) register allows to configure the type of check to be performed on the address and control field contents. 1 buffer is full and is not able to receive a new laps control frame. ctctlbrstx bit tbd laps control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. ctlppdux bit tbd laps frame mapping filter control 0 laps frames are allowed to pass for mapping into sonet/sdh. (default) 1 laps frames are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. ctoffx bit tbd generic laps frame mapping filter control 0 all types of laps frames (i.e., including laps control frames) are allowed to pass for mapping into sonet/sdh. (default) 1 all types of laps frames (i.e., including laps control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only flags (i.e., 0x7e octets) are mapped into sonet/sdh. stctlbx bit tbd laps control frame buffer status indication - 143 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the crsapix register allows to configure the type of check to be performed on the sapi field contents. the crmmaex register allows to configure handling of laps frame with mismatched address or control or sapi field contents. an alarm, arlpsfmmx, is generated when a mismatch is detected on the address or control or sapi field contents of the received laps frame. shared flag (start and closing) detection is configurable. idle flag detection and discard is supported. the crflagx register allows to configure the type of flag detection between consecutive laps frames. self-synchronous de-scrambler (x 43 +1 polynomial) can be enabled or disabled according to the crscrdx register. cracselx bit tbd cracselx bit tbd laps address and control field contents check control 0 0 address and control field contents check is disabled. assume address and control fields are present. 0 1 address and control field contents checked against fixed values (i.e., address=0x04, control=0x03). (default). 1 0 reserved. 1 1 address and control field contents checked against the contents of rracfdx register. crsapix bit tbd laps sapi field contents check control 0 sapi field contents check is disabled. 1 sapi field contents checked against the contents of rrsapfdx register. (default) crmmaex bit tbd laps field contents mismatch management 0 laps frame with mismatched address or control or sapi field contents is discarded. (default) 1 laps frame with mismatched address or control or sapi field contents is not dis- carded crflagx bit tbd laps flag detection control 0 at least two flags to be detected between laps frames. (default). 1 at least a single flag to be detected between laps frames (i.e., a shared flag). crscrdx bit tbd laps descrambling control 0 enable descrambling of laps frame. (default) 1 disable descrambling of laps frame. - 144 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 32-bit fcs generation and checking over all bits of the address, control, sapi, payload information field (shaded area as shown in figure 50 ) not including any flags and abort sequences, is configurable. the crfcs register allows to configure enable/disable laps fcs checking. further, an option is provided to process or discard laps frames with a fcs error according to the crlpfcserx register. an alarm, arlpsfcser, is generated when a laps frame is received with fcs error. for each received laps frame byte that is input to the fcs generator for checking, the bit-order within the byte can be swapped/reversed using the crfcsswapinx register. transparency processing (octet de-stuffing for flags and control escape) is supported. byte de-stuffing occurs between start and closing flags. ability to detect an abort indication via alarm and interrupt generation. to force an abort of the current frame, the crlpabtgx register needs to set to 1. an alarm, arlpsabtdx, is generated when an abort indication is detected (i.e., receive 0x7d followed by 0x7e) on the receive side. processing of invalid laps frames as per itu-t x.86. detection of size (minimum and maximum) of laps payload information field via alarm and interrupt gener- ation. the minimum size of the received laps frame (in octets) can be configured using the rrlpminflx register (i.e., the number of octets between the opening and closing flags). an alarm, arlpsshterx, is generated when the size of received laps frame is less than six octets and this frame is aborted. an alarm, arlpsminerx, is generated when the size of the received laps frame is greater than six octets but less than the value configured in rrlpminflx register. the maximum size of the received laps frame payload crfcsx bit tbd laps fcs check 0 32-bit fcs check is disabled and assume all four fcs field octets are not present. 1 32-bit fcs check is enabled. (default) crlpfcserx bit tbd laps fcs check handling (used when fcs check is enabled as per crfcsx register) 0 received laps frames with fcs error are discarded. (default) 1 received laps frames with fcs error are not discarded. crfcsswapinx bit tbd laps fcs input swap control 0 for each received laps frame byte at the input of the fcs generator, the bit-order is preserved (i.e., not swapped/reversed). (default). 1 for each received laps frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). crlpabtgx bit tbd laps abort generation 0 no frame aborted. (default) 1 current frame under receive is aborted. - 145 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 information field (in octets) can be configured using the rrmaxflx register. an alarm, arlpsmaxerx, is generated when the size of the received laps frame payload information field (in octets) exceeds the value configured in rrmaxflx register. ability to filter and extract laps control frames by the host is supported. a 64-byte buffer (using 64 rrlmix_ (8-0) registers) per mac is provided to store a single laps control frame for the host extraction. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the laps control frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and includ- ing the byte with msb = 0 are not a part of the received frame. the host is provided with a laps control frame such that only the following processing have been performed: fcs check, byte de-stuffing and removal of flags. the srctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the crctlbrstx register. this reset will clear the srctlbx status register (srctlbx=0) and enable a new management/control frame to be received. the rrlpcpx register is used to configure the sapi value to be checked in order to extract the laps control frame and the rrctlmaska1x register is used as a bit level mask that is applied to the crlpcpx register. below is an example of how the host can use this buffer: step 1: if the buffer is empty, srctlbx=0 and the host is not allowed to read for a new laps control frame. step 2: once the laps control frame has been received, the srctlbx status register is set (srctlbx=1) by the ethermap-12 and an alarm, arctlrxx, is generated to indicate that the present laps control frame is ready for extraction by the host. no further laps control frames may be written into the buffer (i.e., are discarded silently) until the srctlbx status register is cleared. if the received laps control frame is bigger than the buffer size, an alarm, arctlberrx, is generated and the buffer must be cleared/reset by the host. step 3: once the laps control frame has been extracted, the srctlbx status register is cleared (srctlbx=0) by the host. this is to indicate that a follow-on received laps control frame may be written into the buffer. rrlpminflx(7-0) laps frame size 0x06 - 0xff indicates minimum number of octets present in a received laps frame between opening and closing flags. (default = 0x06) rrmaxflx(15-0) laps frame payload information field size 0x0001 - 0x2800 indicates maximum number of octets in a received laps frame payload information field. (default = 0x2800) srctlbx bit tbd laps control frame buffer status indication 0 buffer is empty and no new laps control frame has been received/stored. (default) 1 buffer is full with a new laps control frame received. crctlbrstx bit tbd laps control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. - 146 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to filter decapsulation of select laps frames (i.e., frames with sapi field contents equal to rrsapfdx register) that are received from sonet/sdh is provided using crlppdux register. reception of all laps control frames (i.e., control frames destined for extraction by host) are not affected by this register. maintains receive statistics counters. all laps receive side statistic counters are described in ta b l e t b d . rrlpcpx(15-0) laps control frame sapi field contents 0x0000 - 0xffff indicates contents of the laps control frame sapi field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaska1 mask register. (default = 0x0000) rrctlmaska1x(15-0) laps control frame sapi field contents mask 0x0000 - 0xffff mask value that is applied to the rrplcpx register contents to aid in the filtering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrplcpx register is used for filtering. (default = 0xffff) crlppdux bit tbd selective laps frame decapsulation filter control 0 received frames from sonet/sdh, with sapi field contents equal to rrsapfdx register, are allowed to be decapsulated. 1 received frames from sonet/sdh, with sapi field contents equal to rrsapfdx register, are not allowed (i.e., frames are discarded) to be decapsulated. (default) - 147 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 lapf lapf is a hdlc-like framing structure to encapsulate an ieee 802.3 ethernet mac frame to provide a point- to-point full duplex simultaneous bidirectional operation. the lapf protocol is specified in the itu-t q.922 standard. use of lapf for transport of ethernet mac frames is specified in rfc2427. the ethermap-12 device only supports lapf bridged frame format. figure 51 shows the format of a lapf bridged frame with a ethernet mac frame payload (denoted by the shaded area). figure 51. format of lapf bridged frame with an ethernet mac frame payload in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for lapf, the following functions are supported: encapsulate ethernet mac frame within a lapf frame. each ethernet mac frame is encapsulated with a start flag (0x7e), dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui and pid fields, a 16-bit fcs field, and a closing flag (0x7e). field insertions except the start flag can be disabled through configuration according to the ctlfacnopselx register. the insertion of the pad field is also con- figurable using the ctlfpadx register. when other field insertion is enabled, the contents of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui and pid fields are configurable according to the registers described into the ta b l e t b d . msb flag (0x7e) lsb 1 octet msb address (0x04) lsb 1 octet msb control (0x03) lsb 1 octet msb first octet of sapi (0xfe) lsb 1 octet msb second octet of sapi (0x01) lsb 1 octet destination address (da) 6 octets source address (sa) 6 octets length / type 2 octets mac client data 46 - 10000 octets pa d fcs of mac 4 octets fcs of laps 4 octets msb flag (0x7e) lsb 1 octet msb bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb - 148 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 shared flag (start and closing) generation is configurable according to the ctflagx register. idle flag generation and insertion is supported. the ctflagx register allows to configure the minimum number of flags to be inserted between two consecutive lapf frames 16-bit fcs generation over all bits of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui, pid and payload information fields (shaded area as shown in figure 51 ) not including any flags and abort sequences, is configurable using the ctfcsx register. furthermore, the fcs generator can be initialized to a default state using the ctfcsinitiallx register. for each lapf frame byte that is input to the fcs generator, the bit-order within the byte can be swapped/reversed using the ctfcsswapinx register. ctlfacnopselx bit tbd lapf address, control, nlpid, oui and pid field insertion management 0 lapf overhead field content insertion is enabled. (default) address field contents taken from rtdlcix, ctcrx, ctfecnx, ctbecnx and ctdex registers. control field contents taken from rtlfcntlx register. nlpid field contents taken from rtnlpidx register. oui field contents taken from rtouix register. pid field contents taken from rtpidx register. 1 address, control, nlpid, oui and pid field contents insertion is disabled. these fields are all set to zero. ctlfpadx bit tbd lapf pad field insertion management 0 pad field insertion is enabled and the field contents are taken from the rtpadn register. (default) 1 pad field insertion is disabled (i.e., no pad field is present in the lapf frame). ctfcsx bit tbd lapf fcs generation/calculation mode 0 16-bit fcs calculation is disabled and all fcs field octets are not inserted. 1 16-bit fcs calculation is enabled and all fcs field octets are inserted. (default) ctfcsinitiallx bit tbd lapf fcs generator initialization control 0 fcs generator is initialized with an all zeros state. 1 fcs generator is initialized with an all ones state. (default) ctfcsswapinx bit tbd lapf fcs input swap control 0 for each lapf frame byte at the input of the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed). in this case, the least significant bit of each byte is input first into the fcs generator. (default). - 149 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 for each lapf fcs byte from the fcs generator, the bit-order within the fcs byte can be swapped/reversed using the ctfcsswapoutx register before transmission to sonet/sdh. this does not affect the fcs calculation result but rather the transmission bit-order of each fcs byte into sonet/sdh. ability to insert lapf lmi control frames by the host is supported. a 128-byte buffer (using 128 rtctl_x(8- 0) registers) per mac is provided to store a single lapf lmi control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the lapf lmi control frame. the host must write a valid formatted (including overhead bytes) lapf lmi control frame into the buffer such that only additional processing steps performed are: fcs calculation, bit stuffing and addition of flags. the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a lapf lmi control frame. step 2: once the lapf lmi control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the lapf lmi control frame is ready for transmission. step 3: during the next lapf inter-frame window (i.e., after the closing flag of the preceding lapf frame and before the opening flag of the following lapf frame), the stored lapf lmi control frame is inserted into the datapath for transmission to sonet/sdh. step 4: once the lapf lmi control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-12 and an alarm, atctlx, is generated. the alarm can be used to provide an indication of the next available lapf lmi control frame transmission. 1 for each lapf frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). in this case, the most significant bit of each byte is input first into the fcs generator. ctfcsswapoutx bit tbd lapf fcs output swap control 0 for each lapf fcs byte output from the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each lapf fcs byte output from the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being transmit to sonet/sdh. stctlbx bit tbd lapf lmi control frame buffer status indication 0 buffer is empty and is able to receive a new lapf lmi control frame. (default) 1 buffer is full and is not able to receive a new lapf lmi control frame. ctfcsswapinx bit tbd lapf fcs input swap control - 150 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to filter mapping of lapf frames for transmission to sonet/sdh is provided using ctlfpdux register. transmission of all lapf lmi control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of lapf frames (i.e., including lapf lmi control frames) for transmission to sonet/sdh. transparency processing (bit-stuffing for flags and control escape) is supported. bit stuffing occurs between start and closing flags. ability to insert fcs errors for testing is configurable using a self-clearing ctfcsex register (i.e., error is inserted only in a single frame). detection of fifo overflow/underflow conditions and size (maximum) of lapf payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atlfferrx alarm. the limit of the lapf payload information size (in octets) is programmable using the rtmaxflx(15-0) register. an alarm, atlfmaxerx, is generated when the size of the lapf payload information field exceeds the value configured in rtmaxflx register. ctctlbrstx bit tbd lapf lmi control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. ctlfpdux bit tbd lapf frame mapping filter control 0 lapf frames are allowed to pass for mapping into sonet/sdh. (default) 1 lapf frames are not allowed (i.e., frames are discarded) to pass for map- ping into sonet/sdh. ctoffx bit tbd generic lapf frame mapping filter control 0 all types of lapf frames (i.e., including lapf lmi control frames) are allowed to pass for mapping into sonet/sdh. (default) 1 all types of lapf frames (i.e., including lapf lmi control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only flags (i.e., 0x7e octets) are mapped into sonet/sdh. ctfcsex bit tbd lapf fcs error insertion 0 the 16-bit fcs is transmitted without any error insertion. (default) 1 the 16-bit fcs is errored (i.e., inverted) before transmission. rtmaxflx(15-0) lapf payload information field size 0x0001 - 0x2800 indicates maximum number of octets in the lapf payload information field that is transmitted. (default = 0x2800) - 151 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 maintains transmit statistics counters. two types of counters are provided: the total number of lapf frame payloads transmitted (rpctlapfframex register) and the total number of lapf frame payload octets transmitted (rpctlapfbytex register) to sonet/sdh. these are also described in ta b l e t b d. in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for lapf, the following functions are supported: decapsulate to extract the ethernet mac frame from within a lapf frame. field extraction and checking, except the start and closing flags, can be disabled through configuration. when field extraction and checking is enabled, the contents of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui and pid fields of a received lapf frame are validated against configurable stored values. the crlfacnopselx register allows to configure the type of check to performed on the address and control and nlpid and oui and pid field contents. the crlfpadx register allows to configure the type of check to performed on the pad field contents. the crlfmmaex register allows to configure handling of lapf frames with mismatched address or control or pad or nlpid or oui or pid field contents. an alarm, arlfmmx, is generated when a mismatch is detected on the address or control or pad or nlpid or oui or pid field contents of the received lapf frame. crlfacnopselx bit tbd lapf address, control, nlpid, oui and pid field insertion management 0 lapf overhead field content checking is enabled. (default) address field contents are checked against rrlfadrx register. control field contents are checked against rrlfcntlx register. nlpid field contents are checked against rrnlpidx register. oui field contents are checked against rrouix register. pid field contents are checked against rrpidx register. register rrpidx is configured to indicate whether the ethernet frame fcs is present or not. when rrpidx=0x0001, the ethernet frame fcs is present and this ethernet frame is transmitted onto the ethernet line. when rrpidx=0x0007, the ethernet frame fcs is not present and a new ethernet fcs (4-bytes) is generated and appended by the mac before the frame is transmitted onto the ethernet line. 1 address, control, nlpid, oui and pid field contents checking is disabled. crlfpadx bit tbd lapf pad field insertion management 0 lapf pad field contents checking is enabled for only one pad field in the received lapf frame. (default). the pad field contents are checked against rrpadx register. 1 lapf pad field contents checking is disabled. assume no pad field is present in the received lapf frame. - 152 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 shared flag (start and closing) detection is configurable. idle flag detection and discard is supported. the crlfflagx register allows to configure the type of flag detection between consecutive lapf frames. 16-bit fcs generation and checking over all bits of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui, pid and payload information fields (shaded area as shown in figure 51 ) not including any flags and abort sequences, is configurable using the crlffcsx register. further, an option is provided to process or discard lapf frames with a fcs error using the crlffcserx register. an alarm, arlffc- serx, is generated when a lapf frame is received with fcs error. for each received lapf frame byte that is input to the fcs generator for checking, the bit-order within the byte can be swapped/reversed using the crfcsswapinx register. transparency processing (bit de-stuffing for flags and control escape) is supported. bit de-stuffing occurs between start and closing flags. crlfmmaex bit tbd lapf field contents mismatch management 0 lapf frame with mismatched address or control or pad or nlpid or oui or pid field contents is discarded. (default) 1 laps frame with mismatched address or control or pad or nlpid or oui or pid field contents is not discarded crlfflagx bit tbd lapf flag detection 0 at least two flags to be detected between lapf frames. (default). 1 at least a single flag to be detected between lapf frames (i.e., a shared flag). crlffcsx bit tbd lapf fcs check 0 16-bit fcs check is disabled and assume all two fcs field octets are not present. 1 16-bit fcs check is enabled. (default) crlffcserx bit tbd lapf fcs check handling (used when fcs check is enabled as per crlffcsx register) 0 received lapf frames with fcs error are discarded. (default) 1 received lapf frames with fcs error are not discarded. crfcsswapinx bit tbd lapf fcs input swap control 0 for each received lapf frame byte at the input of the fcs generator, the bit-order is preserved (i.e., not swapped/reversed). (default). 1 for each received lapf frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). - 153 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to filter and extract lapf lmi frames by the host is supported. a 520-byte buffer (using 520 rrlmix_(8-0) registers) per mac is provided to store multiple lapf lmi buffer for the host extraction. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the lapf lmi frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and includ- ing the byte with msb = 0 are not a part of the received frame. the host is provided with a lapf lmi frame such that only the following processing have been performed: fcs check, bit de-stuffing and removal of flags. a reset of the buffer can be generated using the crctlbrstx register. this reset will clear the srctlavx status register and causes the 520-byte buffer to clear its present contents. the crlmidlcix register allows to determine the dlci field value to be checked in order to extract the lapf lmi frame. below is an example of how the host can use this buffer: step 1: if the lmi buffer is empty, srctlavx=0 and the host is not allowed to read for a new lapf lmi frame. step 2: once the lapf lmi frame has been received, the srctlavx status register is set (srctlavx=1) by the ethermap-12 to indicate that at least one lapf lmi frame is ready for extraction by the host. further lapf lmi frames may be written into the buffer if received. if so, the srctlavx bit will become set again. an alarm is provided (arctlovf) to indicate the overflow of the 520-byte buffer. ability to detect an abort indication via arlfabtdx alarm and interrupt generation. processing of invalid lapf frames as per itu-t q.922. detection of size (minimum and maximum) of lapf payload information field via alarm and interrupt generation. the minimum size of the received lapf frame (in octets) can be configured using the rrlfminflx register (i.e., the number of octets between the address field and closing flag). an alarm, arlffserx, is generated when the size of received lapf frame is less than three octets (between address field and closing flag) and this frame is aborted. an alarm, arlfminerx, is generated when the size of the received lapf frame is greater than three octets but less than the value configured in rrlfminflx register. the maximum size of the received lapf frame payload information field (in octets) can be configured using the rrmaxflx register. an alarm, arlfmaxerx, is generated when the size of the received lapf frame payload information field (in octets) exceeds the value configured in rrmaxflx register. srctlavx bit tbd lapf lmi frame buffer status indication 0 buffer is empty and no complete lapf lmi frame has been received/stored. (default) 1 buffer is full with at least one complete lapf lmi frame received. crctlbrstx bit tbd lapf lmi frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. crlmidlcix bit tbd lapf lmi dlci field value selection 0 lapf lmi frames with dlci=0 are filtered for extraction by the host. (default) 1 lapf lmi frames with dlci=1023 are filtered for extraction by the host. - 154 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 provide an indication on the status of the lapf link for the receive side. the slnkstsx status register is used by the host to determine the state of the lapf link. after power-up/reset, the lapf link is set to a ? down ? state. while the link is in a ? down ? state, only lapf flags and lmi frames are allowed to be received, furthermore, while in a ? down ? state, when either 64 consecutive lapf flags or a single valid lapf frame are received, the link state is set to an ? up ? state. an alarm, alnkstsupx, is generated to indicate a change of lapf link to an ? up ? state. while the link is in ? up ? state, when 256 consecutive ? 1 ? s are received, the link state is set to a ? down ? state. an alarm, alnkstsdwnx, is generated to indicate a change of lapf link to a ? down ? state. ability to filter decapsulation of lapf frames that are received from sonet/sdh is provided using crlfpdux register. reception of all lapf lmi frames (i.e., control frames destined for extraction by host) are not affected by this register. maintains receive statistics counters. all lapf receive side statistic counters are described in ta b l e t b d . rrlfminflx(7-0) lapf frame size 0x03 - 0xff indicates minimum number of octets present in a received lapf frame between address field and closing flag. (default = 0x06) rrmaxflx(15-0) lapf frame payload information field size 0x0001 - 0x0640 indicates maximum number of octets in a received lapf frame payload information field. (default = 0x0640) crlfpdux bit tbd selective lapf frame decapsulation filter control 0 all lapf frame types received frames from sonet/sdh are allowed to be decapsulated. 1 only lapf lmi frames matching the crlmidlcix register are allowed to be decapsulated. (default) - 155 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ppp (with bcp and lcp support) the point-to-point protocol (ppp) is a hdlc-like framing structure and provides a standard method for transporting multi-protocol datagrams over point-to-point links. ppp can be used to encapsulate ieee 802.3 ethernet mac frame to provide a point-to-point full duplex simultaneous bidirectional operation. the ppp bridging control protocol (bcp) is specified in the following standards: rfc 1661, rfc 1662, rfc 2878 and rfc 2615. figure 52 shows the format of a ppp frame with an ethernet mac frame payload (denoted by the shaded area). figure 52. format of ppp frame with an ethernet mac frame payload in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for ppp, the following functions are supported: encapsulate ethernet mac frame within a ppp frame. each ethernet mac frame is encapsulated with a start flag (0x7e), address, control, ppp protocol, ppp bcp flags, ppp bcp pad and ppp bcp mac type fields, a 16/32-bit ppp fcs field, and a closing flag (0x7e). field insertions except the start flag can be disabled via configuration. when field insertion is enabled, the contents of the address, control, ppp protocol and ppp bcp mac type fields are configurable. the management of the address and control field is performed according to the ctppacselx register. msb flag (0x7e) lsb 1 octet msb address (0xff) lsb 1 octet msb control (0x03) lsb 1 octet msb first octet of ppp protocol (0x00) lsb 1 octet msb second octet of ppp protocol (0x31) lsb 1 octet msb f 0 z b ppp bcp pads lsb 1 octet msb ppp bcp mac type (0x01) lsb 1 octet destination address (da) 6 octets source address (sa) 6 octets length / type 2 octets mac client data 46 - 10000 octets pa d fcs of mac 4 octets fcs of ppp (16/32 bits) 2 or 4 octets msb flag (0x7e) lsb 1 octet msb bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb - 156 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the management of the ppp protocol field is controlled by the ctpppix register. the management of the ppp bcp flag fields (i.e., f, 0, z, b fields) is performed according to the following registers: ctbcpflgfx, ctbcpflg0x, ctbcpflgzx and ctbcpflgbx. ctppacselx bit tbd ctppacselx bit tbd ppp address and control field insertion management 0 0 address and control field contents set to all zeros. 0 1 address and control field contents contain fixed default values (i.e., address=0xff, control=0x03). (default). 10reserved. 1 1 address and control field contents are taken from the rtppacfdx register. ctpppix bit tbd ppp protocol field insertion management 1 ppp protocol field contents set to all zeros. 0 ppp protocol field contents are taken from the rtppfdx register. (default) ctbcpflgfx bit tbd ppp bcp flag f field insertion management 1 ppp bcp flag f field contents set to a one ( ? 1 ? ). (default) 0 ppp bcp flag f field contents set to a zero ( ? 0 ? ). ctbcpflg0x bit tbd ppp bcp flag 0 field insertion management 1 ppp bcp flag 0 field contents set to a one ( ? 1 ? ). 0 ppp bcp flag 0 field contents set to a zero ( ? 0 ? ). (default) ctbcpflgzx bit tbd ppp bcp flag z field insertion management 1 ppp bcp flag z field contents set to a one ( ? 1 ? ). (default) 0 ppp bcp flag z field contents set to a zero ( ? 0 ? ). ctbcpflgbx bit tbd ppp bcp flag b field insertion management 1 ppp bcp flag b field contents set to a one ( ? 1 ? ). 0 ppp bcp flag b field contents set to a zero ( ? 0 ? ). (default) - 157 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the contents of the ppp bcp mac type field is configurable using the rtbcpmacx register. ppp padding mode to be applied is configurable. the rtbcppdmodex register allows to configure the type of padding mode to be used. the ppp padding octet alignment mode (i.e., used when fixed padding mode is enabled) is controlled by the rtbcppdalignx register. the ppp padding octet alignment calculation mode (i.e., used when fixed padding mode is enabled) is controlled by the ctbcppdcalcx register. the contents of the ppp pad octet (i.e., used when fixed padding mode is enabled) is configurable using the rtbcppadx register. rtbcpmacx (15-8) ppp bcp mac type field contents configuration 0x00 - 0xff indicates contents of the ppp bcp mac type field. (default = 0x01) rtbcppdmodex bit tbd rtbcppdmodex bit tbd ppp padding mode control 0 0 no padding is applied. (default) 0 1 a fixed padding mode is enabled. in this mode, the ppp bcp pads field is inserted to indicate the number of pad octets that have been inserted within the ppp frame payload. 10reserved. 11reserved. rtbcppdalignx bit tbd rtbcppdalignx bit tbd ppp padding octet alignment mode control 0 0 a 2 octet alignment boundary is used. (default) 0 1 a 4 octet alignment boundary is used. 1 0 a 8 octet alignment boundary is used. 1 1 a 16 octet alignment boundary is used. ctbcppdcalcx bit tbd ppp padding octet alignment calculation mode control 0 ppp padding octet alignment calculation is over payload area only. (default). 1 ppp padding octet alignment calculation is over entire frame area. (i.e., header, payload and fcs bytes) - 158 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 shared flag (start and closing) generation is configurable. idle flag generation and insertion is supported. the ctflagx register allows to configure the minimum number of flags to be inserted between two consecutive ppp frames. self-synchronous scrambler (x 43 +1 polynomial) can be enabled or disabled. the ctscrdx register allows to enable/disable scrambling of ppp frame. furthermore, the scrambler can be initialized to a default state using the ctscrinitx register. 16 or 32-bit fcs generation over all bits of the address, control, ppp control, ppp bcp flags, ppp bcp pads, ppp bcp mac type, payload information area (shaded area as shown in figure 52 ) and optional pad octet fields not including any opening/closing flags and abort sequences, is configurable using the ctpfcsx register. furthermore, the fcs generator can be initialized to a default state using the ctfcsinitiallx register. rtbcppadx (7-0) ppp pad field contents configuration 0x00 - 0xff indicates contents of the ppp pad octet when fixed padding mode is enabled. (default = 0x00) ctflagx bit tbd ppp flag insertion 0 a single flag are inserted between sequential ppp frames (i.e., a shared flag). 1 minimum of two flags are inserted between two consecutive ppp frames. (default). ctscrdx bit tbd ppp scrambling control 0 enable scrambling of ppp frame. (default) 1 disable scrambling of ppp frame. ctscrinitx bit tbd ppp scrambler initialization control 0 scrambler is initialized with an all zeros state. (default) 1 scrambler is initialized with an all ones state. ctpfcsx bit tbd ctpfcsx bit tbd ppp fcs generation/calculation mode 0 0 16 and 32-bit fcs generation/calculation is disabled. fcs octets are not inserted in the ppp frame. this also applies to any ppp bcp control frames received from the host and for transmission to sonet/sdh. 01reserved. - 159 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 for each ppp frame byte that is input to the fcs generator, the bit-order within the byte can be swapped/reversed using the ctfcsswapinx register. for each ppp fcs byte from the fcs generator, the bit-order within the fcs byte can be swapped/reversed using the ctfcsswapoutx register before transmission to sonet/sdh. this does not affect the fcs calculation result but rather the transmission bit-order of each fcs byte into sonet/sdh. 1 0 only 16 fcs generation/calculation is enabled. two fcs octets are inserted in the ppp frame. this also applies to any ppp bcp control frames received from the host and for transmission to sonet/sdh. 1 1 only 32 fcs generation/calculation is enabled. four fcs octets are inserted in the ppp frame. this also applies to any ppp bcp control frames received from the host and for transmission to sonet/sdh. (default) ctfcsinitiallx bit tbd ppp fcs generator initialization control 0 fcs generator is initialized with an all zeros state. 1 fcs generator is initialized with an all ones state. (default) ctfcsswapinx bit tbd ppp fcs input swap control 0 for each ppp frame byte at the input of the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed). in this case, the least significant bit of each byte is input first into the fcs generator. (default). 1 for each ppp frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice- versa). in this case, the most significant bit of each byte is input first into the fcs generator. ctfcsswapoutx bit tbd ppp fcs output swap control 0 for each ppp fcs byte output from the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each ppp fcs byte output from the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being transmit to sonet/sdh. ctpfcsx bit tbd ctpfcsx bit tbd ppp fcs generation/calculation mode - 160 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to insert fcs errors for testing is configurable using a self-clearing ctfcsex register (i.e., error is inserted only in a single frame). transparency processing (octet stuffing for flags and control escape) is supported. byte stuffing occurs between start and closing flags. stuffing replaces each byte within a ppp frame that matches the flag or control escape code bytes with a two-byte sequence. ability to force abort generation is configurable. the ctabtgx register allows to force (ctabtgx=1) the abortion of the current encapsulated frame by sending 0x7d and 0x7e bytes. detection of fifo overflow/underflow conditions and size (maximum) of ppp payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atppferrx alarm. the limit of the ppp payload information size (in octets) is programmable using the rtmaxflx(15-0) register. an alarm, atppmaxerx, is generated when the size of the ppp payload information field exceeds the value configured in rtmaxflx register. ability to insert ppp link control protocol (lcp)/network control protocol (ncp) control frames by the host is supported. a 128-byte buffer (using 128 rtctl_x(8-0) registers) per mac is provided to store a single ppp lcp/ncp control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the ppp lcp/ncp control frame. the host must write a valid formatted (including overhead bytes) ppp control frame into the buffer such that only additional pro- cessing steps performed are: fcs calculation, byte stuffing, addition of flags and scrambling. the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a ppp lcp/ncp control frame. step 2: once the ppp lcp/ncp control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the ppp lcp/ncp control frame is ready for transmission. step 3: during the next ppp inter-frame window (i.e., after the closing flag of the preceding ppp frame and before the opening flag of the following ppp frame), the stored ppp lcp/ncp control frame is inserted into the datapath for transmission to sonet/sdh. ctfcsex bit tbd ppp fcs error insertion 0 the 16 or 32-bit fcs is transmitted without any error insertion. (default) 1 the 16 or 32-bit fcs is errored (i.e., inverted) before transmission. ctabtgx bit tbd ppp transmit abort generation 0 no abort generated. (default) 1 current frame under transmission is aborted by 0x7d followed by 0x7e. this also applies to any ppp bcp control frames received from the host and for transmission to sonet/sdh. rtmaxflx (15-0) ppp payload information field size 0x0001 - 0x2800 indicates maximum number of octets in the ppp payload information field that is transmitted. (default = 0x2800) - 161 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 step 4: once the ppp lcp/ncp control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-12 and an alarm, atctlx, is generated. the alarm can be used to provide an indication of the next available ppp lcp/ncp control frame transmission. ability to filter mapping of select ppp frames (i.e., frames with ppp protocol field=0x0031) for transmission to sonet/sdh is provided using ctbpdux register. transmission of all ppp lcp/ncp control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of ppp frames (i.e., including ppp lcp/ncp control frames) for transmission to sonet/sdh. maintains transmit statistics counters. two types of counters are provided: the total number of ppp frame payloads transmitted (rpctppframex register) and the total number of ppp frame payload octets transmit- ted (rpctppbytex register) to sonet/sdh. these are also described in ta b l e t b d . in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for ppp, the following functions are supported: stctlbx bit tbd ppp lcp/ncp control frame buffer status indication 0 buffer is empty and is able to receive a new ppp lcp/ncp control frame. (default) 1 buffer is full and is not able to receive a new ppp lcp/ncp control frame. ctctlbrstx bit tbd ppp lcp/ncp control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. ctbpdux bit tbd selective ppp frame mapping filter control 0 ppp frames with ppp protocol field=0x0031 are allowed to pass for map- ping into sonet/sdh. (default) 1 only lcp/ncp-bcp frames from the host are mapped. ctoffx bit tbd generic ppp frame mapping filter control 0 all types of ppp frames (i.e., including ppp lcp/ncp control frames) are allowed to pass for mapping into sonet/sdh. (default) 1 all types of ppp frames (i.e., including ppp lcp/ncp control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only flags (i.e., 0x7e octets) are mapped into sonet/sdh. - 162 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 decapsulate to extract the ethernet mac frame from within a ppp frame. field extraction and checking, except the start and closing flags, can be disabled through configuration. when field extraction and checking is enabled, the contents of the address, control, ppp protocol, ppp bcp flags and ppp bcp mac type fields of a received ppp frame are validated against configurable stored values. further, an option to discard frames with a mismatch of one of the fields, is configurable. the crpacselx register allows to configure the type of check to be performed on the address and control field contents of a received ppp frame. the crpprotx register allows to configure the type of check to be performed on the ppp protocol fields contents of a received ppp frame. the crpfgx register allows to configure the type of check to be performed on the ppp bcp flags field contents of a received ppp frame . the crpmacx register allows to configure the type of check to be performed on the ppp bcp mac type field contents of a received ppp frame . crpacselx bit tbd crpacselx bit tbd ppp address and control field contents check control 0 0 address and control field contents check is disabled. assume address and control fields are present. 0 1 address and control field contents checked against fixed values (i.e., address=0xff, control=0x03). (default). 1 0 reserved. 1 1 address and control field contents checked against the contents of rrpacfdx register. crpprotx bit tbd ppp protocol field contents check control 0 ppp protocol field contents check is disabled. 1 ppp protocol field contents checked against the contents of rrpprotfdx register. (default) crpfgx bit tbd ppp bcp flags field contents check control 0 ppp bcp flags field contents check is disabled. 1 ppp bcp flags field contents checked against the contents of rrpfgfdx register. (default) crpmacx bit tbd ppp bcp mac type field contents check control 0 ppp bcp mac type field contents check is disabled. 1 ppp bcp mac type field contents checked against the contents of rrpmacfdx register. (default) - 163 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the crpacmmaex register allows to configure handling of ppp frame with mismatched address or control field contents. an alarm, arpacmmx, is generated when a mismatch is detected on the address or control field contents of a received ppp frame. the crpprotmmaex register allows to configure handling of ppp frame with mismatched ppp protocol field contents. an alarm, arpprotmmx, is generated when a mismatch is detected on the ppp protocol field contents of a received ppp frame. the crpfgmmaex register allows to configure handling of ppp frame with mismatched ppp bcp flags field contents. an alarm, arpfgmmx, is generated when a mismatch is detected on the ppp bcp flags field contents of a received ppp frame. the crpmacmmaex register allows to configure handling of ppp frame with mismatched ppp bcp mac type field contents. an alarm, arpmacmmx, is generated when a mismatch is detected on the ppp bcp mac type field contents of a received ppp frame. crpacmmaex bit tbd ppp address and control field contents mismatch management 0 ppp frame with mismatched address or control field contents is discarded. (default) 1 ppp frame with mismatched address or control field contents is not discarded. crpprotmmaex bit tbd ppp protocol field contents mismatch management 0 ppp frame with mismatched ppp protocol field contents is discarded. (default) 1 ppp frame with mismatched ppp protocol field contents is not discarded. crpfgmmaex bit tbd ppp pcp flags field contents mismatch management 0 ppp frame with mismatched ppp bcp flags field contents is discarded. (default) 1 ppp frame with mismatched ppp bcp flags field contents is not discarded. crpmacmmaex bit tbd ppp bcp mac type field contents mismatch management 0 ppp frame with mismatched ppp bcp mac type field contents is discarded. (default) 1 ppp frame with mismatched ppp bcp mac type field contents is not discarded. - 164 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 shared flag (start and closing) detection is configurable. idle flag detection and discard is supported. the crflagx register allows to configure the type of flag detection between consecutive ppp frames. self-synchronous de-scrambler (x 43 +1 polynomial) can be enabled or disabled according to the crscrdx register. 16 or 32-bit fcs generation and checking over all bits of the address, control, ppp control, ppp bcp flags, ppp bcp pads, ppp bcp mac type, payload information area (shaded area as shown in figure 52 ) not including any opening/closing flags and abort sequences, is configurable. the crpfcsx register allows to configure enable/disable ppp fcs checking and the crpcrcsx register allows to configure for use of 16 or 32-bit fcs checking. further, an option is provided to process or discard ppp frames with a fcs error according to the crpppcserx register. an alarm, arpppfcser, is generated when a ppp frame is received with fcs error. for each received ppp frame byte that is input to the fcs generator for checking, the bit-order within the byte can be swapped/reversed using the crfcsswapinx register. crflagx bit tbd ppp flag detection control 0 at least two flags to be detected between ppp frames. (default). 1 at least a single flag to be detected between ppp frames (i.e., a shared flag). crscrdx bit tbd ppp descrambling control 0 enable descrambling of ppp frame. (default) 1 disable descrambling of ppp frame. crpfcsx bit tbd ppp fcs check control 0 fcs check is disabled and assume all fcs field octets are not present. 1 fcs check is enabled. (default) crpppcserx bit tbd ppp fcs check handling (used when fcs check is enabled as per crpfcsx register) 0 received ppp frames with fcs error are discarded. (default) 1 received ppp frames with fcs error are not discarded. crpcrcsx bit tbd ppp fcs check type select control 0 32-bit fcs checking used. (default) 1 16-bit fcs checking used. - 165 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 transparency processing (octet de-stuffing for flags and control escape) is supported. byte de-stuffing occurs between start and closing flags. ability to detect an abort indication via alarm and interrupt generation. to force an abort of the current frame, the crpppabtgx register needs to be set to 1. an alarm, arpppabtdx, is generated when an abort indication is detected (i.e., receive 0x7d followed by 0x7e) on the receive side. ability to select type of padding mode used for decapsulation using crbcppdmodex register. processing of invalid ppp frames as per rfc 1662. detection of size (minimum and maximum) of ppp frame via alarm and interrupt generation. the minimum size of the received ppp frame (in octets) can be configured using the rrpppminflx register (i.e., the number of octets between the opening and closing flags). an alarm, arpppshterx, is generated when the size of received ppp frame is less than four (when using 16-bit fcs) or six (when using 32-bit fcs) octets and this frame is aborted. an alarm, arpppminerx, is generated when the size of the received ppp frame is greater than four (when using 16-bit fcs) or six (when using 32-bit fcs) octets but less than the value configured in rrpppminflx register. the maximum size of the received ppp frame payload informa- tion field (in octets) can be configured using the rrmaxflx register. an alarm, arpppmaxerx, is gener- ated when the size of the received ppp frame payload information field (in octets) exceeds the value configured in rrmaxflx register. crfcsswapinx bit tbd ppp fcs input swap control 0 for each received ppp frame byte at the input of the fcs generator, the bit- order is preserved (i.e., not swapped/reversed). (default). 1 for each received ppp frame byte at the input of the fcs generator, the bit- order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). crpppabtgx bit tbd ppp abort generation 0 no frame aborted. (default) 1 current frame under receive is aborted. crbcppdmodex bit tbd ppp padding mode control 0 a fixed padding mode is used. 1 no padding is used. (default) rrpppminflx(7-0) ppp frame size 0x04 - 0xff indicates minimum number of octets present in a received ppp frame between opening and closing flags. (default = 0x04 when using 16-bit fcs or 0x06 when using 32-bit fcs) - 166 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to filter and extract ppp lcp/ncp control frames by the host is supported. a 520-byte buffer (using 520 rrlmix_ (8-0) registers) per mac is provided to store a single ppp lcp/ncp control frame for the host extraction. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the ppp lcp/ncp control frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and including the byte with msb = 0 are not a part of the received frame. the host is pro- vided with a ppp lcp/ncp control frame such that only the following processing have been performed: fcs check, byte de-stuffing and removal of flags. a reset of the buffer can be generated using the crctl- brstx register. this reset will clear the srctlavx status register and causes the 520-byte buffer to clear its present contents. the rrplcpx register is used to configure the ppp protocol field value to be checked in order to extract the ppp lcp control frame and the rrctlmaska1x register is used as a bit level mask that is applied to the crplcpx register. the rrpncpx register is used to configure the ppp protocol field value to be checked in order to extract the ppp ncp control frame and the rrctlmaskb1x register is used as a bit level mask that is applied to the crpncpx register. below is an example of how the host can use this buffer: step 1: if the buffer is empty, srctlavx=0 and the host is not allowed to read for a new ppp lcp/ncp control frame. step 2: once the ppp lcp/ncp control frame has been received, the srctlavx status register is set (srctlavx=1) by the ethermap-12 to indicate at least one ppp lcp/ncp control frame is ready for extraction by the host. further ppp lcp/ncp control frames may be written into the buffer if received. if so, the srctclavx bit will become set again. an alarm is provided (arctlovf) to indicate the overflow of the 520-byte buffer. rrmaxflx(15-0) ppp frame payload information field size 0x0001 - 0x2800 indicates maximum number of octets in a received ppp frame payload information field. (default = 0x2800) srctlavx bit tbd ppp lcp/ncp control frame buffer status indication 0 buffer is empty and no complete ppp lcp/ncp control frame has been received/stored. (default) 1 buffer is full with at least one complete ppp lcp/ncp control frame received. crctlbrstx bit tbd ppp lcp/ncp control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. rrplcpx(15-0) ppp lcp control frame ppp protocol field contents 0x0000 - 0xffff indicates contents of the lcp control frame ppp protocol field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaska1 mask register. (default = 0xc021) rrctlmaska1x(15-0) ppp lcp control frame ppp protocol field contents mask 0x0000 - 0xffff mask value that is applied to the rrplcpx register contents to aid in the filtering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrplcpx register is used for filtering. (default = 0xffff) - 167 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ability to filter decapsulation of select ppp frames (i.e., frames with ppp protocol field=0x0031) that are received from sonet/sdh is provided using crbpdux register. reception of all ppp lcp/ncp control frames (i.e., control frames destined for extraction by host) are not affected by this register. maintains receive statistics counters. all ppp receive side statistic counters are described in table tbd . rrpncpx(15-0) ppp ncp control frame ppp protocol field contents 0x0000 - 0xffff indicates contents of the ncp control frame ppp protocol field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaskb1 mask register. (default = 0x8031) rrctlmaskb1x(15-0) ppp ncp control frame ppp protocol field contents mask 0x0000 - 0xffff mask value that is applied to the rrpncpx register contents to aid in the filtering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrpncpx register is used for filtering. (default = 0xffff) crbpdux bit tbd selective ppp frame decapsulation filter control 0 received frames from sonet/sdh, with ppp protocol field=0x0031, are allowed to be decapsulated. 1 received frames from sonet/sdh, with ppp protocol field=0x0031, are not allowed (i.e., frames are discarded) to be decapsulated. (default) - 168 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 transparent hdlc the transparent hdlc is a generic hdlc-like framing structure and provides a standard method for transporting multi-protocol datagrams over hdlc links. figure 53 shows the format of a transparent hdlc frame with an ethernet mac frame payload (denoted by the shaded area). figure 53. format of transparent hdlc frame with an ethernet mac frame payload in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for transparent hdlc, the following functions are supported: a pre-configured/encapsulated ethernet mac frame within a transparent hdlc frame is provided by the external client (i.e the hdlc overhead byte(s) have already been configured by the external client). each transparent hdlc frame is encapsulated with a start flag (0x7e), a 16/32-bit fcs field, and a clos- ing flag (0x7e). no other field insertions are allowed except the start flag. shared flag (start and closing) generation is configurable. idle flag generation and insertion is supported. the ctflagx register allows to configure the minimum number of flags to be inserted between two consecutive transparent hdlc frames. self-synchronous scrambler (x 43 +1 polynomial) can be enabled or disabled. the ctscrdx register allows to enable/disable scrambling of transparent hdlc frame. furthermore, the scrambler can be initialized to a default state using the ctscrinitx register. msb flag (0x7e) lsb 1 octet msb hdlc overhead byte 1 lsb 1 octet msb hdlc overhead byte 2 lsb 1 octet msb hdlc overhead byte 3 lsb 1 octet msb hdlc overhead byte 4 lsb 1 octet msb hdlc overhead byte 5 lsb 1 octet msb hdlc overhead byte n (1=< n=< 15) lsb 1 octet destination address (da) 6 octets source address (sa) 6 octets length / type 2 octets mac client data 46 - 10000 octets pa d fcs of mac 4 octets fcs of hdlc (16/32 bits) 2 or 4 octets msb flag (0x7e) lsb 1 octet msb bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb - 169 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 16 or 32-bit fcs generation over all bits of the hdlc overhead bytes, payload information area (shaded area as shown in figure 53 ) not including any opening/closing flags and abort sequences, is configurable using the ctpfcsx register. furthermore, the fcs generator can be initialized to a default state using the ctfcsinitiallx register. for each transparent hdlc frame byte that is input to the fcs generator, the bit-order within the byte can be swapped/reversed using the ctfcsswapinx register. for each transparent hdlc fcs byte from the fcs generator, the bit-order within the fcs byte can be swapped/reversed using the ctfcsswapoutx register before transmission to sonet/sdh. this does not affect the fcs calculation result but rather the transmission bit-order of each fcs byte into sonet/sdh. ability to insert fcs errors for testing is configurable using a self-clearing ctfcsex register (i.e., error is inserted only in a single frame). transparency processing (octet stuffing for flags and control escape) is supported. byte stuffing occurs between start and closing flags. stuffing replaces each byte within a transparent hdlc frame that matches the flag or control escape code bytes with a two-byte sequence. ability to force abort generation is configurable. the ctabtgx register allows to force (ctabtgx=1) the abortion of the current encapsulated frame by sending 0x7d and 0x7e bytes. detection of fifo overflow/underflow conditions and size (maximum) of transparent hdlc payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atppferrx alarm. the limit of the transparent hdlc payload information size (in octets) is programmable using the rtmaxflx(15-0) register. an alarm, atppmaxerx, is generated when the size of the transparent hdlc payload information field exceeds the value configured in rtmaxflx register. maintains transmit statistics counters. two types of counters are provided: the total number of transparent hdlc frame payloads transmitted (rpctppframex register) and the total number of transparent hdlc frame payload octets transmitted (rpctppbytex register) to sonet/sdh. in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for transparent hdlc, the following functions are supported: shared flag (start and closing) detection is configurable. idle flag detection and discard is supported. the crflagx register allows to configure the type of flag detection between consecutive transparent hdlc frames. self-synchronous de-scrambler (x 43 +1 polynomial) can be enabled or disabled according to the crscrdx register. 16 or 32-bit fcs generation and checking over all bits of the hdlc overhead bytes, payload information area (shaded area as shown in figure 53 ) not including any opening/closing flags and abort sequences, is configurable. the crpfcsx register allows to configure enable/disable fcs checking and the crpcrcsx register allows to configure for use of 16 or 32-bit fcs checking. further, an option is provided to process or discard transparent hdlc frames with a fcs error according to the crpppcserx register. an alarm, arpppfcser, is generated when a transparent hdlc frame is received with fcs error. for each received transparent hdlc frame byte that is input to the fcs generator for checking, the bit- order within the byte can be swapped/reversed using the crfcsswapinx register. transparency processing (octet de-stuffing for flags and control escape) is supported. byte de-stuffing occurs between start and closing flags. ability to detect an abort indication via alarm and interrupt generation. to force an abort of the current frame, the crpppabtgx register needs to be set to 1. an alarm, arpppabtdx, is generated when an abort indication is detected (i.e., receive 0x7d followed by 0x7e) on the receive side. processing of invalid transparent hdlc frames as per rfc 1662. - 170 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 detection of size (minimum and maximum) of transparent hdlc payload information field via alarm and interrupt generation. the minimum size of the received transparent hdlc frame (in octets) can be config- ured using the rrpppminflx register (i.e., the number of octets between the opening and closing flags). an alarm, arpppshterx, is generated when the size of received transparent hdlc frame is less than four (when using 16-bit fcs) or six (when using 32-bit fcs) octets and this frame is aborted. an alarm, arpppminerx, is generated when the size of the received transparent hdlc frame is greater than four (when using 16-bit fcs) or six (when using 32-bit fcs) octets but less than the value configured in rrppp- minflx register. the maximum size of the received transparent hdlc frame (in octets) can be configured using the rrmaxflx register. an alarm, arpppmaxerx, is generated when the size of the received trans- parent hdlc frame (in octets) exceeds the value configured in rrmaxflx register. maintains receive statistics counters. - 171 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 gmii mux-mode this mode is used in applications which require a single external gigabit ethernet client to transfer ethernet frames into multiple vcgs in the sonet/sdh side. figure 54 below provides an overview of the gmii mux- mode application. figure 54. gmii mux-mode application overview multiplexing packets for independent multiple sonet/sdh side vcgs across a single gmii interface has two major components that are addressed by ethermap-12: an addressing scheme utilizing a destination vcg id included with the mac frame assigned by the external source side of the gmii interface identifying the traffic source. the vcg id is optionally removed by the ethermap-12, before transmission to sonet/sdh, to recover the original ethernet mac frame. a modified and flexible 802.3 pause control frame payload to specify xon/xoff on a per vcg basis. each vcg ? s tx fifo fill levels are monitored for filling beyond a threshold. exceeding the threshold results in a pause frame sent to the opposite mac client asserting the xoff state for the tx fifo that is experiencing congestion. when the tx fifo returns below a minimum threshold, a second pause frame is sent to the opposite mac client asserting the xon state for the tx fifo that is relieved of congestion. lastly, the gmii mux-mode is allowed to be independently configured for both ethernet-to-sonet/sdh and sonet/sdh-to-ethernet directions. ethermap-12 mac client gbe interface mux-mode pause frame for upstream layer-2/3 npu mac client downstream gbe upstream gbe encapsulated mac frame, downstream encapsulated mac frame, upstream -rx flow control monitor -tx mac side -rx mac side upstream tx fifos downstream fifos downstream rx buffers upstream tx buffers multiple sonet/sdh side vcgs ? statistical mux ? like processing of gmii vcg ? s vcg id insertion - 172 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 sdram controllers sdram memory interfaces these interfaces are used to allow the mapper to connect two external sdram memory modules. the external sdram memory modules are used for buffering of ethernet traffic in both directions. each of the external sdram memory interfaces comprises of a 32-bit data bus, 13-bit address bus, bank address bus, 3- bit command bus, input/output mask bus, system clock (up to 125 mhz) and control enable signals. the sdram control blocks will interface to a dynamic random access memory containing up to 256 mbits. they will support a quad-bank sdram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). the external sdrams will be accessed as 4 banks with a data bus width of 32 bits. read and write accesses to the external sdrams are burst oriented using alternative bank switching. access starts at a selected location and continues for a programmed number of locations in a programmed sequence. access begins with issuing an active command, which is then followed by a read or write command. the address bits issued together with the active command are used to select the bank and row to be accessed. the address bits issued together with the read or write command are used to select the starting column location for the burst access. the sdram interface blocks will require programmable read or write burst lengths of 2 locations with or without a burst terminate option. an auto precharge function may be enabled, to initiate a self-timed row precharge, at the end of the burst sequence. the 256 mb sdram interface blocks may change the row/column address on every clock cycle, in order to achieve a high-speed, fully random access. one bank in precharged while accessing one of the other three banks, thus hiding the precharge cycles and providing high-speed, random-access operation. the 256 mb sdram control blocks will operate with 3.3v, low-power memory block. all inputs and outputs are lvttl-compatible. cas latency please refer to timing diagrams sdram_read, sdram_write. the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the sdram interface can be programmed for a latency of three clock cycles. this means that data will be sampled on the third rising edge after the read command is issued. bank/row activation please refer to timing diagrams sdram_read, sdram_write. the active command is issued before any read or write. after issuing the active command, the read or write command may be issued to the selected row, subject to the trcd specification. the sdram block controller is designed for sdram having a trrp (min) lower than 16 ns; with a clock rate of 125 mhz. this implies that a read or write command can be issued on the second rising edge after the active command was issued. - 173 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 commands the following commands can be issued by the sdram controllers (see the table below): reset configuration of sdram controller upon reset the sdram controller is configured for a 4 bank 256 mbit sdram. the default configuration parameters are: sdram size: 256 mbits. auto refresh period: sdram_trfc = 7. sdram auto refresh period (expressed in 8 periods of sysclk input): sdrarp = 78 (decimal) which creates a 5 s/row auto refresh period. precharge command period: sdram_trp = 2 (cannot be changed). power-up initialization delay: sdrtinit = 100. indicates 100 units of 100 periods of the sysclk input, in other words, 10000 times sysclk. it is required by the sdram prior to issuing any command other than a command inhibit or a nop. number of auto refresh performed during initialization (full sdram auto-refresh): sdrinit_ar_mbr = 8. a configured value of 'n' will provide 'n+1' auto refresh cycles during the initialization period. mode register default value: mbr_value = 0 000 011 0 001. configuration changes/initialization after power-up, or in order to change any of the sdram configuration parameter, the following procedure must be used: modify the sdrarp (address tbd), sdrinit_ar_mbr (address tbd) and/or sdrtinit (address tbd) registers. write the csdram register (address tbd) with sdram_cfg and sdram_trfc new values (if no change, use default values) and with sdraminit field at 1. all the configuration registers dedicated to the sdram controller are described in table tbd of the memory map. command name cs ras cas we mask addr bk notes command inhibit nop h x x x x x x no operation nop l h h h x x x active l l h h x bank/row read l h l h l/h bank/col write l h l l l/h bank/col valid precharge l l h l x code x auto or self refresh l l l h x x x load mode register l l l l x op-code x write enable l active write inhibit h high z - 174 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 microprocessor access to sdram here is the procedure to perform a write access to the sdram: write the data to write in the 2 sixteen-bits registers up_data2wrmsb (address tbd) and up_data2wrlsb (address tbd). write the address to write in the up_addr2wrmsb (bits tbd to tbd of tbd register) and up_addr2wrlsb (16 bits of tbd register) registers. set to 1 the up_wraddr2wr register (bit tbd of tbd register). this bit is cleared by the chip at the end of the sdram write access. here is the procedure to perform a read access to the sdram: write the address to read in the up_addr2rdmsb (bits tbd to tbd of tbd register) and up_addr2rdlsb (16 bits of tbd register) registers. set to 1 the up_wraddr2rd register (bit tbd of tbd register). this bit is cleared at the end of the sdram read access. when the up_wraddr2rd is cleared, the data is available in the up_datardlsb register (tbd address) for the lsb value and up_datardmsb register (tbd address) for the msb value. all the registers for access of the sdrams with the microprocessor, are described in the tables tbd of the memory map. - 175 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 reset operation general four types of reset are available in this device, external lead controlled hardware reset, microprocessor controlled hardware reset, microprocessor soft reset and microprocessor controlled global performance counters reset. external lead controlled hardware reset the reset external lead activates the hardware reset. the actions are as follows: the configuration bits are in default state (all ethernet mac disabled, sdram 256 mb configuration, encapsulation/de-encapsulation in laps mode, all the vt/vc are not allocated to any vcg, the telecom bus interface is disabled) all the interrupt bit mask are in disabling state all the performance counters are cleared microprocessor controlled hardware reset when the reseth byte register (bits tbd of register tbd) is equal to 91 hex, it activates the hardware reset. the actions are the same as the external lead controlled hardware reset. to clear the reset action, it is necessary to change the value of the reseth byte register (bits tbd of register tbd) or to perform an external lead controller hardware reset. microprocessor controlled soft reset sixteen soft reset are available in the device, eight for each direction (ethernet to sonet/sdh and sonet/sdh to ethernet). the tx_resetsx byte registers (bits tbd of registers tbd-tbd) are corresponding to the software reset of the ethernet line #0 to #7 in the transmit direction. the rx_resetsx byte registers (bits tbd of registers tbd-tbd) are corresponding to the software reset of the vcg #0 to #7 in the receive direction. when the value of the byte register of each software reset is equal to 91 hex, it activates the corresponding software reset. the actions are as follows: all the internal logic is initialized no impact on the control/configuration registers or counters to clear the reset action, it is necessary to change the value of the corresponding software reset byte register or to perform an external lead controller hardware reset or to activate the microprocessor controlled hardware reset (reseth). please note that the soft reset must be kept asserted for 16 s before releasing it. the tx_resetsx needs to be activated and then deactivated whenever the corresponding l1aptrramerrx alarm in register tbd becomes set to avoid a potential lockup condition. microprocessor controlled global performance counter reset when the resetc byte register (bits tbd of register tbd) is equal to 91 hex, it activates the global performance counter reset. the main actions is to clear all the performance counters. to clear the reset action, it is necessary to change the value of the global performance counter reset byte register or to perform an external lead controller hardware reset or to activate the microprocessor controlled hardware reset (reseth). the reset action can also be cleared by the global software rest or any of the 16 per channel software resets. - 176 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 telecom bus operation general when the ethermap-12 is configured for drop timing, the add bus is byte and multi-frame synchronous with the drop bus, although delayed by one byte time because of internal processing. for example, if a byte in the stm-4 vc-4 structure using tug-3, tu-12 mapping is to be added to the add bus, the time of its placement is derived from the drop bus timing, and from software instructions specifying which tu-12 number is being added. note that the tu-12 drop selection can be different than the add bus selection. an option is provided which enables the drop bus timing signals to be sent as outputs on the add bus. when the device is configured for add bus timing, the add bus data, parity, and add indicator can be either derived from the input add bus clock, c1j1v1, and spe signals, or derived from internally generated and outputted clock, c1j1v1, and spe signals. drop bus interface the drop bus consists of the following leads: input data (tbdd(7-0)), input parity (tbdpar), input clock (dclk), input c1, j1, and optional v1 marker pulses (tbdc1j1v1), input payload indication (tbdspe). the most significant bit (msb) of the input data is assigned to tbdd7. the msb is defined as the first bit received in a sonet/sdh byte (i.e., bit 1 in the sonet/sdh byte). the bus rate is 77.76 mhz. the drop bus is monitored for loss of clock. the loss of drop clock alarm is alossdclk at bit tbd of register (tbd). - 177 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 drop bus parity selection the parity selection for the drop bus is according to the following table. a parity error is indicated by the parityerror alarm at bit tbd of register (tbd). other than an alarm indication, no action is taken by the ethermap-12. add bus interface the add bus consists of the following leads: output data (tbad(7-0)), output parity (tbapar), output add-to-bus indicator (tbadd ) the timing information can be input or output: input/output c1, j1, and optional v1 marker pulses (tbac1j1v1), input/output payload indication (tbaspe). the most significant bit (msb) of the output data is assigned to tbad7. the msb is defined as the first bit transmitted in a sonet/sdh byte (i.e., bit 1 in the sonet/sdh byte). the bus rate is 77.76 mhz. the add bus is always synchronous to the rtclk reference clock. parityeven (bit tbd of register tbd) paritymode (bit tbd of register tbd) drop bus parity selection 0 0 odd parity is calculated for the data input leads (dd(7-0)). 0 1 odd parity is calculated for the input leads consisting of data (dd(7-0)), clock (dclk), c1, j1, and v1 marker pulses (dc1j1v1), and the payload indicator (dspe). 1 0 even parity is calculated for the input leads consisting of data (dd(7-0)), clock (dclk), c1, j1, and v1 marker pulses (dc1j1v1), and the payload indicator (dspe). 1 1 even parity is calculated for the data input leads (dd(7-0)). - 178 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 add bus timing modes the add bus interface configuration and timing modes are shown in the following table. the tbmode lead selects the c1j1v1, and spe signals to be either inputs or outputs. the tbmaster lead allows the c1j1v1, and spe signals to be tristated. the data (tbad(7-0)), parity (tbadpar), and add indicator (tbadd ) leads are always output and their direction is not dependent on the timing mode chosen. tbmode tbmaster add bus configuration and timing mode 0 x add bus timing slave mode: the c1, j1, v1 marker pulses (tbac1j1v1), and payload indicator (tbaspe) are inputs. 1 0 add bus timing master mode: the c1, j1, v1 marker pulses (tbac1j1v1), and payload indicator (tbaspe) are outputs. 1 1 add bus timing master mode: the c1, j1, v1 marker pulses (tbac1j1v1), and payload indicator (tbaspe) are tristated. - 179 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 add bus parity selection the parity selection for the add bus is according to the following table. note that the timing mode selected for the add bus must be consistent with the parity mode selected. add indicator invert an option is provided for inverting the active level of the add indicator signal (add lead). when a 0 is written to control bit addind_actlow (bit tbd, register tbd), the add signal is high when payload is being added to the bus. when a 1 is written to control bit addind_actlow, the add signal is low when payload is being added to the bus. this control bit defaults to a 1 upon power-up or via software reset. add bus delay options for additional delay of the add bus data, parity, add indicator, and optionally the c1j1v1 and spe signals, relative to either the add bus or drop bus timing are shown in the following table. control field timingdelay can delay the add bus outputs by up to fifteen extra clock cycles. all add bus outputs are delayed one clock from the timing when control field timingdelay is set to 0, for all timing modes except the add bus mode in which the timing signals are outputs. for this mode there is always no delay between the output data and timing. add bus delay is used to align added data and timing when used in add bus timing mode with a transwitch overhead terminator such as the phast ? -12n. parityeven (bit tbd, register tbd) paritymode (bit tbd, register tbd) add bus parity selection 0 0 odd parity is calculated for the data output leads (ad(7-0)). 0 1 odd parity is calculated for the output leads consisting of data (ad(7-0)), clock (aclk), c1, j1, and v1 marker pulses (ac1j1v1), and the payload indicator (aspe). 1 0 even parity is calculated for the data output leads (ad(7-0)). 1 1 even parity is calculated for output leads consisting of data (ad(7-0)), clock (aclk), c1, j1, and v1 marker pulses (ac1j1v1), and the payload indicator (aspe). timingdelay (bits tbd, register tbd) timing mode add bus additional delay 0-f drop bus; add bus timing out- puts tristated. add bus data, parity, and add indicator additional delay is up to 15 clocks from the drop bus timing. 0-f drop bus; add bus timing out- puts active. add bus data, parity, add indicator, c1j1v1, and spe additional delay is up to 15 clocks from the drop bus timing. 0-f add bus; add bus timing sig- nals are inputs. add bus data, parity, and add indicator additional delay is up to 15 clocks from the add bus timing. - 180 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 force vc-3 or vc-4 time slots to high impedance the data, parity, and add indicator corresponding to a vc-3 can be forced to a high impedance state by setting control bit highz_au3 at bit tbd of register tbd (vc-3 #1), tbd (vc-3 #2), or tbd (vc-3 #3) to a 1. when operating in the au-4 mode (control bit au_mode, bit tbd in register tbd is a 1), the data, parity, and add indicator for the vc-4 can be forced to a high impedance state by setting all three highz_au3 control bits to a 1. force tug-3 time slots to high impedance when operating in the au-4 mode (control bit au_mode, bit tbd in register tbd is a 1), the data, parity, and add indicator corresponding to a tug-3 can be forced to a high impedance state by setting control bit highz_tug3 at bit tbd of register tbd (tug-3 #1), tbd (tug-3 #2), or tbd (tug-3 #3) to a 1. force tug-2 time slots to high impedance the data, parity, and add indicator corresponding to a tug-2 can be forced to a high impedance state by setting control bit highz at bit tbd of register tbd (tug-2 #1), tbd (tug-2 #2), tbd (tug-2 #3),... or tbd (tug-2 #21) to a 1. force tu-11/tu-12 time slots to high impedance the data, parity, and add indicator corresponding to a tu-11 can be forced to a high impedance state by setting control bit highz at bit tbd of register tbd (tu-11 #1), tbd (tu-11 #2), tbd (tu-11 #3),... or tbd (tu-11 #84) to a 1. the data, parity, and add indicator corresponding to a tu-12 can be forced to a high impedance state by setting control bit highz at bit tbd of register tbd (tu-12 #1), tbd (tu-12 #2), tbd (tu-12 #3),... or tbd (tu-12 #63) to a 1. 0-f add bus; add bus timing sig- nals are outputs. add bus additional delay control is disabled. timingdelay (bits tbd, register tbd) timing mode add bus additional delay - 181 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 boundary scan introduction the boundary scan interface block provides a five-lead test access port (tap) that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test. the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides absorbability and controllability for the interface leads of the device. as shown in figure 55 , one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). the boundary scan capability is based on a test access port (tap) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. the boundary scan test bus interface consists of four input signals (test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs t ) and a test data output (tdo) output signal. boundary scan signal timing is shown figure 35 . the tap controller receives external control information via a test clock (tck) signal and a test mode select (tms) signal, and sends control signals to the internal scan paths. detailed information on the operation of this state machine can be found in the ieee 1149.1 standard. the serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. these three serial registers are connected in parallel between the test data input (tdi) and test data output (tdo) signals, as shown in figure 55 . the boundary scan function can be reset and disabled by holding lead trs t low. when boundary scan testing is not being performed, the boundary scan register is transparent, allowing the input and output signals to pass to and from the ethermap-12 device ? s internal logic. during boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. boundary scan operation the maximum frequency the ethermap-12 device will support for boundary scan is 10 mhz. the timing diagrams for the boundary scan interface leads are shown in figure 35 . the instruction register contains three bits. the ethermap-12 device performs the following three boundary scan test instructions: the extest test instruction (000) provides the ability to test the connectivity of the ethermap-12 device to external circuitry. the sample test instruction (010) provides the ability to examine the boundary scan register contents without interfering with device operation. the bypass test instruction (111) provides the ability to bypass the ethermap-12 boundary scan and instruction registers. boundary scan reset specific control of the trst lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-up of the ethermap- 12. if boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the v il requirements listed in the ? input, output and input/output parameters ? section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor. - 182 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 55. boundary scan schematic tap controller bypass register instruction register tdi tdo in out controls boundary scan serial test data core logic of ethermap-12 boundary scan register signal input and output leads 3 device - 183 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 alarms, performance and fault monitoring this section details out the alarm/status and performance monitoring features for the ethermap-12 device. the general features are described herein, with specific listing of all alarms, performance counters appearing in the relevant sections. terminology system alarm (raw, unlatched alarm) a signal that traces in real time, the evolution of a system property (a system fault, statistic, or any other characteristic that needs monitoring) when appropriately enabled. this signal, then can be monitored for purposes of corrective action or for the purposes of status reporting. note that the terms system alarm, raw alarm or unlatched alarm may be used interchangeably. alarm event a transition in the state of a system alarm. note that there can be two types of transitions in a system alarm - a rising edge, or a falling edge corresponding to ? alarm entry ? or ? alarm exit ? respectively. latched alarm a latched alarm for a given unlatched alarm, is the associated latched memory for the occurrence of an alarm event (of a single type, or either type) in the unlatched alarm signal. this permits processing of the system alarm without real-time constraints. the active transition or level, which leads to setting of the latched alarm, in general may be software configurable. secondary alarm inhibition the process of filtering to provide data reduction and unnecessary generation of interrupts, when an alarm event that is at a higher hierarchy leads to the generation of multiple lower order alarms (in other words, lower order alarm events are triggered as a secondary effect). this filtering mechanism (termed herein as ? secondary alarm inhibition) prevents redundant data processing and also the unnecessary interrupt burden that may affect adversely the functioning of the system. notes: - refer section 6 of [g806], relating to defect correlations. - the alarm inhibition function may be built at the unlatched alarm level, or, if gr-253 style reporting requirements need to be supported, then the alarm inhibition may be built at the latched alarm level. trail signal failure (tsf) see [g806] server signal failure (ssf) see [g806] - 184 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 interrupt mask if interrupt generation is a function of a given latched alarm, there will be a corresponding dedicated interrupt mask bit, that may be set up to disable the particular interrupt. these bits will be software readable and writable. performance and fault monitoring (pm and fm) an unlatched alarm may have associated with it a corresponding pm/fm feature, that allows a system to monitor the long term evolution of the particular alarm, in a convenient manner. as an example (refer [gr253] section 6), a system may wish to monitor if a defect occurred over only a single unit time interval, or, if the defect persisted over several unit time intervals with respect to a certain particular alarm, or a group of alarms. the unit time interval may be 1-second, or any other, as laid down by applicable standards (if any), or as required to implement a specified performance and fault monitoring system. performance monitoring (pm) for transwitch devices, the 1-second pm output bit associated with an unlatched alarm indicates the occurrence of an alarm event over the immediately preceding 1-second interval. fault monitoring (fm) for transwitch devices, the 1-second fm output bit associated with an unlatched alarm indicates that the unlatched alarm was continuously asserted, without any alarm events taking place, over the duration of at least the immediately preceding 1-second interval. 1-second clock the 1-second clock defines 1-second time intervals to serve as a time reference for the pm/fm scheme (see onesec page tbd-leads table). this clock typically, may be provided from external sources to transwitch devices, and is also used to synchronize the external polling mechanism that would query the pm/fm registers on the transwitch device. performance counters certain alarm events or parameters are counted for system performance monitoring. the counter width (in bits) depends on the event being counted, and time-intervals (that is, estimated maximum counts) between reads. the performance counters may adopt one of two schemes: a. counters that either roll-over or saturate. here ? roll-over ? means that after the terminal count is reached, the counter wraps around, and continues to count from zero; ? saturate ? means that after terminal count is reached, the counter stops incrementing, and freezes at the terminal count. b. counters that clear on 1-second boundaries, with existing counts over the 1-second interval transferred to 1- second counter shadow registers (also on the 1-second boundaries). the main event counters are cleared by the microprocessor writing 0 ? s to the counter, or at 1-second boundaries. counter scheme (a) is more appropriate if the pm/fm system is not implemented. scheme (b) is conceptually compatible with the pm/fm system. however, there will be no constraint imposed by this specification in implementing either counter scheme. the implementation of the desired counter scheme is governed by the particular device specification. - 185 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 unlatched alarms all unlatched alarms are memory mapped and available to be read out from read-only type registers for the actual status. the unlatched alarm signal is active high only when asserted. these signals may be logically grouped together for easy microprocessor readout on a per channel basis, or based on any other appropriate grouping. however, whatever the grouping arrangement is adopted for the unlatched alarm signals, the same grouping is applied for the associated latched alarms, mask bits, and pm/fm bits. unlatched alarms can be both frame based, like sonet/sdh performance alarms, or, independent of framing, such as loss of signal alarms, or buffer overflow/underflow alarms etc. inhibition of secondary unlatched alarm generation the generation of secondary unlatched alarm may be inhibited dynamically, depending on system alarm hierarchy to prevent unnecessary automatic reporting of secondary alarms which arise as a consequence of some primary root cause alarm (the particular inhibiting conditions for a given device). this process is known as ? defect correlation ? in [g806]. defect correlation will also inhibit the generation of unnecessary interrupts at a lower layer. refer figures 6.1 and 6.2 in [g806], that illustrate the process of alarm supervision and defect correlation at each atomic function. each atomic function generates ais as appropriate, based on locally detected defects only. upstream ais or upstream tsf/ssf signals are inputs to the atomic function. the defect correlation process in [g806] terminology is described as c(defect) <--- d(defect) and (not(inhibition_condition) and (inhibition_enabled)) there are two components for the inhibition function: 1) active high alarm inhibition condition based on upstream or primary or root cause alarms; (active_hi_alarm_inhibition_cond). this includes possibly an upstream tsf/ssf. 2) static, software configurable bit inhib_alarm_name_en, that enables such a correlation. note that provision for the inhib_alarm_name_en control bit is optional. on power up, or on a hw reset, this control bit is set up with a zero. the presence of this control gives the system the flexibility to implement defect correlation. the correlated defect (unlatched alarm generated after being operated on by the inhibition function) gives rise to two possible sets of latched alarm event bits, discussed below. latched alarms every unlatched alarm bit (alarm_name) has a corresponding latched alarm bit for interrupt generation (called lalarm_name, if there is no associated pm/fm). if there is performance and fault monitoring associated with an unlatched alarm, then there are two separate latched alarm bits: (1) one for generating hardware/software interrupts (called l1alarm_name); and (2) another to be used for pm/fm circuits (called l2alarm_name) for pm and fm functionality. it should be noted that it is not necessary for pm/fm to be associated with every unlatched alarm, while a latched alarm must exist for every unlatched alarm. the purpose of the latched alarm(s) is two-fold: 1. to generate a hardware or software interrupt to flag the occurrence of an alarm event to the external host processor or to an on-chip processor. 2. to derive the performance and fault monitoring (pm/fm) conditions. the l1alarm_name bits are latched read-only (r(l)), cleared on a microprocessor read (or on a system reset). the l2alarm_name bits, for pm/fm, are read/write, cleared either by the microprocessor writing a zero to this bit, or on 1-second clock boundaries (or on system reset). - 186 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 the general scheme for latched alarm processing is shown below. latched alarm bits for interrupt generation (lalarm_name/l1alarm_name) the ethermap-12 is capable of latching according to the states given in the following table. inrt(1-0) (actual symbol names are cinrt_grp125m (table tbd, on page tbd), cinrt_grp100m (table tbd, on page tbd), cinrt_grptx20m (table tbd, on page tbd), cinrt_grprx20m (table tbd, on page tbd) and cinrt_sotern_core (table tbd, on page tbd)) are global configuration bits for the group of latched alarm bits for interrupt generation (labelled as lalarm_name in systems without pm/fm, for example llos; and labelled as l1alarm_name in systems with pm/fm, for example l1los). the case for level triggering is included for completeness; most transwitch devices are doing away with that option. at minimum, all transwitch devices are configurable for the positive edge only and positive/negative edge events. the negative edge only and the level triggering events are additional optional features of particular devices, to be specified in the device top level frs. for devices that does not incorporate these options, the inrt(1-0) = (0,0) or (1,0) settings are invalid. table 5: latched alarm bit (l1alarm_name) transition selection software access to this set of latched alarm bits is as follows: normal operation: latched read only, and clears on a microprocessor read, or on global resets. test mode: normal read/write, and clear on a micro read, or on global resets. it is possible to write a 1 to any latched bit position. there is a global top level device test mode control bit, distributed to all constituent ip cores that defaults to 0 on power up or hw reset. all l /l1alarm_name values are readable by software, before application of masking. the following diagram of figure 56 illustrates the above described options. inrt1 inrt0 action 0 0 all latched alarm bits (event bits) latch on the positive level (i.e., true state) of the unlatched alarm. when a latched alarm bit position is cleared, it re- latches if the unlatched alarm is still active (true). (this mode is no longer favored in transwitch devices; the only purpose of its inclusion is when pm/fm is not provided, this may be one option of monitoring a persistent fault). 0 1 all latched alarm bits (event bits) latch on the positive transition of an unlatched alarm. when a latched alarm bit position is cleared, it remains reset unless the alarm goes inactive and then active again. this is expected to be the most frequently used mode for the latched alarm bits. 1 0 all latched alarm bits (event bits) latch on the negative transition of an unlatched alarm. when a latched alarm bit position is cleared, it remains reset unless the alarm goes active and then inactive again. the purpose of these bits is added flexibility, in configuring all events for alarm exit conditions. 1 1 all latched alarm bits (event bits) latch on either the positive or negative transition of an unlatched alarm. when a latched alarm bit position is cleared, it remains reset unless the alarm transitions again. - 187 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 56. latched alarm bit (l1alarm_name) transitions latched alarm masking bits (malarm_name) each latched alarm l/l1alarm_name has its own static masking bit that is software configurable, and is named malarm_name. the latched alarm combined with the state of the mask bit may generate an interrupt. these individual interrupts are grouped at various levels of hierarchy (with masking provided at each level) and finally be consolidated at a top level software polling register. depending on individual device requirements, there could also be a single global interrupt mask bit. the hardware interrupt capability is enabled by writing a 1 into the hinten control bit. when disabled, the hardware interrupt indication int/irq lead is tristated (for a device/chip-level output) or, at the ip core level, the o_int/irq signal is in the inactive state, even when a latched indication (event) bit is set. a software polling bit and the hardware interrupt state (when enabled by writing a 1 to hinten) indication occurs when one or more positive level inrt1, inrt0=00 clear on read alarm bit (unlatched) event bit (latched) alarm bit (unlatched) alarm bit (unlatched) event bit (latched) event bit (latched) positive transition inrt1, inrt0=01 negative transition inrt1, inrt0=10 set on pos. transition clear on read set on neg. transition clear on read alarm bit (unlatched) event bit (latched) positive/negative transition inrt1, inrt0=11 set on transition clear on read - 188 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 bit locations in the interrupt mask bit locations are written with a ? 0 ? , and the corresponding latched alarm occurs. note that the polarity of the int/irq output signal for the intel/motorola processor interface is selectable by selecting the appropriate microprocessor interface (not in the scope of the present specification). please note that setting of a mask bit to 0 enables the actions by an alarm. the hardware interrupt state is exited when any one (or more) of the following occurs: hinten control bit is written with a 0 alarm mask bit is written with a 1 latched alarm bit position is cleared the software polling indication is zero when any one (or more) of the following occurs: alarm mask bit is written with a 1 latched alarm bit position is cleared please note that a latched alarm will re-latch if the alarm is active for a positive level transition. secondary latched alarm inhibition the process of ? defect correlation ? in [g806] (refer section 3.2.1 for references to defect correlation), maybe done at the latched alarm level. this process is optional to the process described in section 3.2.1. note the difference: the process in section 3.2.1 suppresses generation of the unlatched alarms, whereas, this process allows the unlatched alarm to be generated. the latched alarm is inhibited dynamically, depending on system alarm hierarchy to prevent unnecessary automatic latching of secondary alarms which arise as a consequence of some primary root cause alarm. the above inhibits the generation of unnecessary interrupts, while at the same time, allow the monitoring of the secondary alarms for optional report generation, as certain standards require, since the unlatched alarms are readable, and their generation is not suppressed (as an example of such a standard, the bellcore/telcordia gr-253, sept. 2000: section 6.2.1.8.4, r6-293 and r6-294, may be cited). there are three components for the function: 1) active high alarm inhibition condition based on upstream or primary or root cause alarms; (active_hi_alarm_inhibition_cond). 2) static, software configurable bit inhib_alarm_name_en, that enables such an inhibit (note that provision for the inhib_alarm_name_en control bit is optional). on power up, or on a hw reset, this control bit is set up with a zero. 3) delayed release of unlatched alarm signal for interrupt generation when the inhibition condition for the secondary latched alarm is removed ( ? off-delay ? timer). this blocks the generated secondary alarm for sufficiently long duration so that its delayed exit after the exit of the primary alarm is kept from actuating the secondary latched event. for example, for a vt demapper, the vt ais alarm exit could take 3 sonet/sdh multiframes, or 1.5 milliseconds to integrate. if an upstream ais alarm is used to inhibit the vt ais alarm, the inhibit function could stay in effect for 1.5 ms after the upstream ais alarm exits. the unlatched alarm when not blocked by the inhibition function, gives rise to two possible sets of latched alarm event bits, discussed above and below. - 189 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 latched alarm bits for pm/fm (l2alarm_name), performance monitoring (pm bits; palarm_name) and fault monitoring (fm bits; falarm_name) the latched alarm bits for pm/fm are capable of latching according to the states given in the following table. lpf(1-0) are global configuration bits for the group of latched event bits for pm/fm. these bits are named l2alarm_name, corresponding to the unlatched alarm, alarm_name. also, the corresponding pm and fm bits are named palarm_name and falarm_name (as an example, the pm/fm bits for the oof alarm is called poof and foof respectively). software access to this set of latched event bits: normal mode: latched read only; writable for 0's only. these latched event bits for pm/fm are cleared by writing them with a zero by the microprocessor, or, on 1-second clock rising edges, or on global resets. writing 1 ? s have no effect. test mode: normal read/write. are cleared on writing them with a zero by the microprocessor, or, on 1-second clock rising edges, or on global resets. masking does not apply to these bits. however, inhibition does apply. pm/fm registers have a hierarchy that is identical to the basic system alarm hierarchy, that governs the interrupt hierarchy. note that 1-second interval boundaries are used to determine the state of a given alarm or event over the immediately preceding 1-second interval; whether an alarm persisted for multiple seconds; to obtain 1-second performance counts; and to operate the 1-second performance and fault monitoring registers, and performance counter shadow registers. the 1-second clock may be an external input, that is distributed globally throughout the device, or, obtained inside the device as a derivative of some other external reference input. the 1-second clock input is synchronized with respect to the time base that the host microprocessor uses to initiate the 1-second reads. it is extremely important that this be so since otherwise, pm/fm data and performance counts may be lost. the table below shows the action of these control bits, in selection of the active transition in the main unlatched alarm for setting the latched event bits: table 6: latched alarm bit (l2alarm_name) transition selection the pm/fm latched event bit and the main unlatched alarm together set up the pm/fm indication bits as shown in the following timing diagrams, for all the three active options of the lpf(1-0). the pm/fm 1-second shadow registers are enabled with the control bit srgen set to 1. this control bit also enables the 1-second pm counter shadow registers if applicable. note that the pm/fm registers can be cleared either by the microprocessor writing zeros to these locations of the memory map, or on the rising edges of the 1-second clock. lpf1 lpf0 action 00 latched status bits for pm/fm disabled. 01 latched status indication sets on positive alarm transition. 10 latched status indication sets on negative alarm transition. 11 latched status indication sets on both positive and negative alarm transitions. - 190 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 positive edge events the following diagram shows the case for the rising edge transition in the example unlatched alarm, loss of signal (los). assuming that control bits lpf(1-0) = 01, the transition from 0 to 1 of the los alarm will cause the l2los bit to latch. (the alarm status can be determined by reading periodically the unlatched alarm status bit, until it becomes 0, indicating that recovery has taken place). assume that the pm/fm shadow registers are enabled. then on rising edges of the input 1-second clock, the pm indication bit plos is set to indicate (a) the unlatched alarm entered in the preceding 1-second interval, or (b) the current unlatched alarm was active for at least the entire preceding 1-second interval. in addition, the fm indication bit flos is set if the alarm is active, but the transition to the active state did not occur in the last 1-second interval (i.e., the alarm has persisted for longer than 1-second). the rising edge of the 1-second pulse is also reset the latched event bit position l2los independent of the microprocessor. note that plos is set on rising edge of the 1-second clock, when, los+l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that even if the duration of the fault event is much smaller than the 1- second interval, the plos signal captures it. note also that flos is set on rising edge of the 1-second clock, when, los&l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that flos is set on a 1-second edge, only if the unlatched alarm was active, without the transition having occurred in the immediately previous interval. hence, the combination plos&flos = 1 is interpreted as an alarm entry in the immediately previous interval; and flos = 1 shows a persistent fault. figure 57. positive edge event - pm/fm signal generation one sec. pulse los l2los plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (input) note 1: for this example, latched events are set only on positive event transitions. note 2: plos = los + l2los evaluated at 1-second boundaries (where ? + ? is a logical or). note 3: flos = los & l2los evaluated at 1-second boundaries (where ? & ? is a logical and, and x is a logical inversion). - 191 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 negative edge events the following diagram shows the case for the falling edge transition in the example unlatched alarm, loss of signal (los). assuming that control bits lpf(1-0) = 10, the transition from 1 to 0 of the los alarm causes the l2los bit to latch. the l2los alarm event now signifies an alarm exit. as in the previous case for the rising edge transition, the alarm status can be determined by periodically reading the unlatched alarm status bit, until it becomes 0, indicating that recovery has taken place. assume that the pm/fm shadow registers are enabled. then, on rising edges of the input 1-second clock, the pm indication bit plos is set to indicate either: (a) the unlatched alarm exited in the preceding 1-second interval, or (b) the current unlatched alarm was active for at least the entire preceding 1-second interval. for the negative transition case, the fm indication bit flos is set if the alarm is active, and the alarm did not clear in the last 1-second interval. the rising edge of the 1-second pulse is also reset the latched event bit position l2los independent of the microprocessor. note that plos is set on rising edge of the 1-second clock, when, los+l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that even if the duration of the fault event is much smaller than the 1- second interval, the plos signal captures it. note also that flos is set on rising edge of the 1-second clock, when, los&l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that flos is set on a 1-second edge, only if the unlatched alarm was active, without the negative edge transition having occurred in the immediately previous interval. hence, for the neg edge event, the combination plos&flos = 1 is interpreted as the alarm los cleared in the immediately previous interval; and flos = 1 shows a persistent fault, or the unlatched alarm occurred in the previous interval. figure 58. negative edge event - pm/fm signal generation one sec. pulse los l2los plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (input) note 1: for this example, latched events are set only on negative event transitions. note 2: plos = los + l2los evaluated at 1-second boundaries (where ? + ? is a logical or). note 3: flos = los & l2los evaluated at 1-second boundaries (where ? & ? is a logical and, and x is a logical inversion). - 192 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 positive or negative edge events the following diagram shows the case for the rising or falling edge transition in the example unlatched alarm, loss of signal (los). assuming that control bits lpf(1-0) = 11, the transition from 1 to 0, or, from 0 to 1, of the los alarm causes the l2los bit to latch. the l2los event now signifies either an alarm entry or exit. the alarm status can, as in the previous cases, be determined by reading periodically the unlatched alarm status bit, until it becomes 0, indicating that recovery has taken place. assume that the pm/fm shadow registers are enabled. then, as before (for the rising edge only or falling edge only cases), on rising edges of the input 1-second clock, the pm indication bit plos is set to indicate either: (a) there was an alarm event, either entry or exit, in the unlatched alarm in the previous 1-second interval; or (b) the unlatched alarm has been asserted over the past 1-second interval. for the positive or negative transition case, the fm indication bit flos is set if the alarm is active, and the alarm did not enter or clear in the last 1- second interval (i.e., the alarm has persisted for longer than 1-second). the rising edge of the 1-second pulse is also reset the latched event bit position l2los independent of the microprocessor. note that plos is set on rising edge of the 1-second clock, when, los+l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that even if the duration of the fault event is much smaller than the 1- second interval, the plos signal captures it. note also that flos is set on rising edge of the 1-second clock, when, los&l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that flos is set on a 1-second edge, only if the unlatched alarm was active, without the transition having occurred in the immediately previous interval. hence, for the pos or neg edge event, the combination plos&flos = 1 is interpreted as the alarm los entered or cleared in the immediately previous interval; and flos = 1 shows a persistent fault, with the unlatched alarm transition, pos- itive or negative, not having occurred in the previous interval. figure 59. positive/negative edge event - pm/fm signal generation one sec. pulse los l2los plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (input) note 1: for this example, latched events are set on positive or negative event transitions. note 2: plos = los + l2los evaluated at 1-second boundaries (where ? + ? is a logical or). note 3: flos = los & l2los evaluated at 1-second boundaries (where ? & ? is a logical and, and x is a logical inversion). - 193 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 overall alarm generation and pm/fm process diagram the following is a signal flow diagram that illustrates the process of generating the l1alarm_name and l2alarm_name bits from the common starting input of the unlatched alarm (alarm_name). the diagram is based on the alarm inhibition process. included is a basic view of the logic diagram used for setting the software polling bits and the hardware interrupt (where & is an ? and ? function, and + is an ? or ? function), using the l1alarm_name, and the corresponding mask bit. note the diagram shows a simplified situation, without any hierarchies. the ? off delay ? is the time for which the inverter output is held low after the alarm inhibition condition is removed (when inhib_alarm_name_en = 1). a clock together with a counter could be used to realize this delay; the clock is such that counter sizes are minimized, while providing the appropriate level of granularity, so that the smallest required delay can be realized efficiently. the pm/fm bit generation starting from the l2alarm_name bit is included. note that both the l1alarm_name and the l2alarm_name bits are subject to the same inhibiting condition. figure 60. alarm, interrupt and pm/fm generation process if the alarm inhibition function is adopted, then the signal simplifies as follows: figure 61. alarm, interrupt and pm/fm generation process (inhibition function) + & & latched alarm hinten=1(hardware interrupt enabled) software polling bit hardware interrupt (raw) unlatched alarm (alarm_name) inhib_alarm_name_en = 0 active_hi_alarm_inhibition_cond & inv & other_latched_unmasked_alarms (l1alarm_name) latched alarm (l2alarm_name) pm/fm gen. block delay off- edge cfg 1: edge cfg 2: inrt (1-0) lpf (1-0) (palarm_name) (falarm_name) pm fm mask bit (malarm_name) = 0 + latched alarm hinten=1(hardware interrupt enabled) software polling bit hardware interrupt (correlated) unlatched alarm (alarm_name) & & other_latched_unmasked_alarms (l1alarm_name) latched alarm (l2alarm_name) pm/fm gen. block edge cfg 1: edge cfg 2: inrt (1-0) lpf (1-0) (palarm_name) (falarm_name) pm fm mask bit (malarm_name) = 0 (see [g806] fig 6.1 and 6.2) defect correlator active_hi_alarm_inhibition_cond (includes inhib_alarm_name_en tsf/ssf) - 194 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 performance counters performance counters in the ethermap-12 device use two different schemes, as dictated by their respective functions: scheme a - counters with roll-over/saturation option these performance counters are configurable to be either saturating or non-saturating. when the performance counters are configured to be saturating, the counters stop at their maximum count. in the saturating mode, counts that occur during a micro read cycle, are held off and the counter updates later. a saturating counter is reset to zero on a microprocessor read cycle. when the performance counters are configured to be non-saturating they roll over to 0 on the next count after the maximum count is reached (i.e., all ones). in this mode, the counters do not clear on a microprocessor read cycle, but continue to count. when a ? reset counters ? operation is performed, these performance counters are set to an all-zeros value. this type of counter is used in the following two areas: the encapsulation and decapsulation blocks, with performance counters described in tables (tbd). control bit crov (address tbd) selects between saturate and roll-over. the ethernet mac blocks, with performance counters described in tables (tbd). control bit autoz (address tbd) selects between saturate and roll-over. all performance counters may be reset simultaneously by writing a 91h to top level register resetc. all counters in the device that can be read by the microprocessor, are of the 'read/write' type, and for test pur- poses, the microprocessor is able to write any value to them. a status alarm bit count with an associated interrupt mask bit mcount is provided. the count status bit is set when any of the performance counters has reached its maximum value in the saturating mode of operation only. when a microprocessor reads the saturated counter, the counter is cleared, but the latched alarm (lcount) is not cleared unless read and cleared separately. scheme b - performance counters with 1-second shadow register option the differences from scheme a, are: 1. there are designated bits (1 bit for each counter) available, that take up counter overflow, for each counter. 2. in the event that a terminal count is reached, the overflow bit is used as an indicator. there is no equivalent of the crov configuration bit as in the case of scheme a. 3. the counters can only be cleared by the rising edge of a 1-second interval boundary, or, if the microprocessor writes 0 ? s to the counters. the counters are reset to all 0 ? s. 4. at the 1-second boundary, the contents of the performance counter are transferred, along with the overflow indication bit, to a 1-second shadow register for the particular counter, after which the counter is cleared. thus, the 1-second shadow register for the performance counter updates only on 1-second boundaries. 5. the 1-second shadow registers are enabled with the common shadow register enable control bit, srgen. 6. there is no equivalent of the count alarm, for saturated counter operation, as with scheme a. clearing/resetting of performance counters in scheme b, is accomplished in a manner similar to that of scheme a. the shadow register holds its count during a microprocessor read cycle. however, the main performance counters may be updated internally on a coincident 1-second boundary, for a count update. this type of counter is used in the tx mapper and rx demapper block. - 195 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 alarm feature combinations each defined system alarm or event, have associated with it one of the following groups of features: group 1: a main unlatched alarm signal (alarm_name). a latched alarm indication an unlatched alarm, for the purpose of status and interrupt generation (l1alarm_name). latched alarm interrupt mask bit (malarm_name). group 2: features group 1. a latched alarm indication for an unlatched alarm, for the purpose of 1-second performance and fault monitoring (l2alarm_name). 1-second pm bit (palarm_name). 1-second fm bit (falarm_name). group 3: features group 1. performance counter. group 4: features group 2. performance counter. group 5: performance counter only; note that there may be performance counters that are not associated with any alarm (for example, sonet/sdh pointer justification counters). group 6: a latched alarm indication for the main unlatched system alarm or event, for the purpose of 1-second performance and fault monitoring (alarm 2). 1-second pm bit. 1-second fm bit. performance counter. it is the responsibility of the individual device ? s specification to completely specify for each alarm, the following: 1. group of features applicable. 2. main unlatched alarm entry condition, with standard reference if applicable. 3. main unlatched alarm exit condition, with standard reference if applicable. - 196 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 4. alarm action. 5. hierarchical position of the alarm, that is what secondary alarms and performance counter(s) are inhibited on its occurrence. 6. the decision to implement a scheme a or scheme b performance counters (on a per counter basis, if applicable). 7. inhibition definition, inhibition extension times, and enable control bits as applicable. system alarm, interrupt, and pm/fm hierarchy the system alarm and interrupt hierarchy are device specific, and aimed towards providing a convenient software interrupt nesting, so that poll times are considerably reduced. the pm/fm registers follow a similar hierarchy, only difference being that the pm/fm bits are not subject to masking (they are subject to inhibition however). in general, the alarm and interrupt hierarchy follow one or more of the following grouping schemes: protocol layers, example for sonet/sdh devices, section layer, line/ho path layer, lo path layer. channel numbers (example, alarms/masks grouped based on vt numbers for hdm, or channel numbers for framers etc.). alarm functionality (e.g., global alarm for a vt lop condition). receive/transmit or other special hierarchical groupings). each latched alarm bit has a mask bit. in addition, depending on the grouping chosen, each hierarchical level has a consolidated latched alarm and associated mask; may also have pm/fm bits, depending on alarm feature group specified. the software polling interrupt register provides a way to have the processor poll a register in memory (provided the proper interrupt mask disable bits are set) to indicate the alarms that causes the interrupt or the alarms that are set without having to read all the alarm registers until the active alarm is found. there is also a hierarchical alarm inhibition scheme that may be implemented, based on needs and standards. the diagram of figure 62 below illustrates how an alarm and interrupt hierarchy is to be achieved: - 197 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 figure 62. alarm interrupt hierarchy hinten=1(hardware interrupt enabled) hardware interrupt & + & latched alarm mask bit = 0 software polling bit unlatched alarm & alarm inhibit + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit (group #1) for group # 1 & & + + mask bit = 0 group # 1 software polling bit for group # 2 mask bit = 0 group # 2 software polling bit for group # 3 mask bit = 0 group # 3 overall ip core mask bit = 0 overall ip core software polling bit note : (1) depending on actual needs, there may be several polling bits from a given ip block. this figure shows the concept of hierarchy in a simplified manner. + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit (group #2) + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit (group #3) (up readable) (up readable) (up readable) (2) based on device specification, there can be a single global mask bit that can disable the hw interrupt for the entire device. & & + - 198 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 mapper/demapper performance monitoring pointer adjustment counters per level 3 high order path: - incoming positive pointer adjustment count, - incoming negative pointer adjustment count. pointer adjustment counters per low order path: - incoming positive pointer adjustment count, - incoming negative pointer adjustment count. poh counters per high order path: - b3 near-end errored bip count, - b3 near-end errored block count, - g1 far-end error count, configurable to count either rei errors or errored blocks, - near-end defect second, - far-end defect second. poh counters per low order path: - v5 near-end errored bip count, - v5 near-end errored block count, - v5 far-end errored block count, - near-end defect second, - far-end defect second. all performance counters are one second shadow registers and at the one second boundary, the contents of each performance counter is latched into its one second shadow register, after which the performance counter is cleared. these one second shadow registers will hold their value during the entire period between two subsequent one second boundaries. the one second shadow registers are available for software read-only access. all performance counters are saturating: counting will stop when the maximum count value is reached. all errored bip and block counters are dimensioned to cover the maximum count value during a one second interval meaning they can never reach saturation. - 199 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 package information the ethermap-12 device is packaged in a 27 millimeter (mm) 27 mm, 580-lead plastic ball grid array (pbga) suitable for surface mounting, as shown in figure 63 . figure 63. ethermap-12 txc-04212 package diagram b e e1 dimension (note 1) nominal notes: 1. all dimensions are in millimeters. values shown are for refer- ence only. 2. identification of the solder ball a1 corner is contained within this shaded zone. this package corner may be a 90 angle, or chamfered for a1 identification. 3. size of array: 26 x 26, jedec code mo-151. a a1 a2 2.23 nom. 0.5 1.17 a3 (ref.) 0.56 nom. b (ref.) 0.63 + .07/- 0.13 d27.0 d1 (bsc) 25.0 d2 25 e27.0 e1 (bsc) 25.0 e2 25 e (bsc) 1.0 bottom view d d2 note 2 e1/4 d1/4 transwitch txc-04212aiog e e2 a rpnm kjhgfedcb tl u ac ab aa y w v ae ad af 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 23 22 10 24 25 26 d1 a2 a3 a a1 58 51 58 51 58 51 58 51 - 200 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ordering information part number: txc-04212aiog 580-lead plastic ball grid array package (pbga) related products txc-03453b, tl3m device (triple level 3 mapper). maps three 44.736 mbit/s ds3 to an stm-1, tug- 3 or sts-3 sts-1 spe sdh/sonet signal. an 34.368 mbit/s e3 signal is mapped in to an stm-1 tug-3. the tl3m ? s sdh/sonet interface format is combus, byte wide parallel. the tl3m supports drop bus and add bus sdh/sonet timing modes. drop bus timing provides timing signals for the add side while timing for both busses is independent for the add bus timing mode. txc-04222, temx28 device (21/28 channel dual bus high density mapper). an add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. up to 28 e1, ds1, or vt/tu payloads are mapped to and from vt1.5/tu-11s and vt2/tu-12s carried in an stm-1 vc-4 or sts-3 format. txc-04226b, ethermap-3 device (ethernet into sts-3/stm-1 sonet/sdh mapper). the ethermap- 3 is a highly integrated device that provides for mapping of 10/100/1000 mbit/s ethernet into sonet/sdh sts-3/stm-1 transport payloads. the device supports connection for up to eight 10/100 mbit/s ethernet ports, using smii interfaces, or a single 1000 mbit/s ethernet port, using a gmii interface. in the transmit direction, for each port, received ethernet frames are encapsulated using either gfp, laps or lapf protocol. txc-06103, phast-3n device (sdh/sonet stm-1, sts-3 or sts-3c overhead terminator) this phast-3n device provides a telecom bus interface for downstream devices and operates from a power supply of 3.3 volts. txc-06212, phast-12e device (programmable, high-performance atm/packet/transmission sonet/sdh terminator for level 12). a highly integrated sonet/sdh terminator device designed for atm cell, frame, higher-order multiplexing, and transmission applications. this phast-12 device provides a telecom bus interface for downstream devices and operates from a power supply of 3.3 volts. txc-06312, phast-12n device (stm-4/oc-12 sdh/sonet overhead terminator with telecom bus interface). a highly integrated sdh/sonet overhead terminator device designed for tdm payload mappings. a single phast-12n can terminate four individual stm-1/oc-3 lines or a single stm-4/oc-12 line. each sdh/sonet terminator has a line interface block that performs clock synthesis and clock recovery for four 155 mbit/s signals or a single 622 mbit/s serial signal. txc-06603, pop-12 device (oc-12 sonet/sdh path overhead processor, retimer, and cross connect). the pop-12 integrates vc-3/vc-4 poh processing, au-3/au-4 pointer processing retiming, and vc-3/vc-4 cross connect for four telecom bus interfaces into one package. it provides an interface to high density mapper applications when used with the transwitch phast-12e (txc-06212), and mapper and framer devices. the pop-12 device is designed to provide a seamless interface to the phast-12e device. txc-06840, envoy-8fe device (octal fast ethernet controller). the envoy-8fe device is a serial media independent interface (smii) to pos-phy level 2/3 interface converter transporting ethernet packets. envoy-8fe has 8 smii ports. packet data from the 8 ports are aggregated onto the pos-phy interface. txc-06842, envoy-2ge device (dual gigabit ethernet controller). the envoy-2ge device is a gigabit media independent interface (gmii) to pos-phy level 2/3 interface converter transporting ethernet packets. envoy-2ge has 2 gmii ports. packet data from the 2 ports are aggregated onto the pos-phy interface. - 201 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 reference documents [1] mpc8260 powerquicc user ? s manual, mpc8260um, 4/1999, rev. d [2] mpc8260 powerquicc user ? s manual errata, mpc8260umad/d, 10/2002, rev 6 [3] mpc8260 gpcm timing diagram, app. note, 8/2000, rev. 1.0 - 202 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 25 west 43 rd street fax: (212) 398-0023 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 404 balboa street tel: (415) 561-6275 san francisco, ca 94118 fax: (415) 561-6120 web: www.atmforum.com atm forum europe office kingsland house - 5 th floor tel: 20 7837 7882 361-373 city road fax: 20 7417 7500 london ec1 1pq, england atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt (see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (303) 397-7956 (outside u.s.a.) 15 inverness way east fax: (303) 397-2740 englewood, co 80112 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 00 fax: 4 93 65 47 16 650 route des lucioles web: www.etsi.org 06921 sophia-antipolis cedex, france go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (903) 769-3818 washington, dc 20007 web: www.mvip.org - 203 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 ieee (corporate office): american institute of electrical engineers tel: (212) 419-7900 (within u.s.a.) 3 park avenue, 17th floor tel: (800) 678-4333 (members only) new york, new york 10016-5997 u.s.a. fax: (212) 752-4929 web: www.ieee.org itu-t (international): publication services of international telecommunication union tel: 22 730 5852 fax: 22 730 5853 telecommunication standardization sector web: www.itu.int place des nations, ch 1211 geneve 20, switzerland jedec (international): joint electron device engineering council tel: (703) 907-7559 2500 wilson boulevard fax: (703) 907-7583 arlington, va 22201-3834 web: www.jedec.org mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 fax: (215) 697-1462 building 4 / section d web: www.dodssp.daps.mil 700 robbins avenue philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 5440 sw westgate dr., #217 tel: (503) 291-2569 (outside u.s.a.) portland, or 97221 fax: (503) 297-1090 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-2673 (within u.s.a.) attention - customer service tel: (732) 699-2000 (outside u.s.a.) 8 corporate place rm 3a184 fax: (732) 336-2559 piscataway, nj 08854-4157 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunication technology committee tel: 3 3432 1551 fax: 3 3432 1553 hamamatsu-cho suzuki building web: www.ttc.or.jp 1-2-11, hamamatsu-cho, minato-ku tokyo 105-0013, japan - 204 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 list of data sheet changes this change list identifies those areas within this updated ethermap-12 device data sheet that have significant differences relative to the previous and now superseded ethermap-12 data sheet: updated ethermap-12 device data sheet: product preview edition 2, november 2003 previous ethermap-12 device data sheet: product preview edition 1a, june 2003 the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. where occurred changed 0640 to 2800, 64-byte to 128-byte and 64-byte to 520-byte. 10 changed last bullet of ? tx and rx eos processors ? section. 11 added last bullet to ? 10/100/1000 mbps ethernet mac blocks ? section. changed fourth bullet of ? sdram interfaces ? section. changed ? microprocessor interface ? section. 12 changed the diagram of figure 1 . 13 changed ? block diagram description ? section. 14 changed ? sdram memory interfaces ? section. 22 - 44 added ? lead no ? for its ? symbol ? . 24 changed name/functions for symbols tbac1j1v1 and tbadd . 25 changed paragraph above table. changed type and name/function for symbol etntxgclk. changed name/function for symbol etntxen. 26 changed name/functions for symbols etnrxdv, etnrxclk, etnmdio and etnmdc. 28 changed name/function for symbol sd1clka. 31 changed name/function for symbol sd2clka. 33 changed name/function for symbol pohtxdle1. 36 changed note below ? host processor interface selection ? table. 43 changed symbol for lead no. ae5. changed name/functions for symbols testin7- testin0 and testout7-testout0. 44 changed name/function for symbol scanin39-scanin8. 45 changed tbd to 16 in the ? thermal characteristics ? table. 46 - 49 updated ? input, output and input/output parameters ? section. 50 changed notes 2 and 3. 51 added note 4 and changed notes 2 and 3. 53 added note 4 and changed notes 2 and 3. 54 changed min and max values, and unit for symbol t pwh . 55 changed title of figure 12 . changed unit for symbol t pwh in the table. 56 changed title of figure 13 . 58 changed the diagram of figure 15 and the table. - 205 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 59 changed the diagram of figure 16 and the table. 60 added new figure 17 and the table. 61 added new figure 18 and the table. 66 corrected the diagram of figure 23 and changed notes 2 and 3. 67 corrected the diagram of figure 24 . 68 corrected the diagram of figure 25 and changed notes 1 and 2. 69 corrected the diagram of figure 26 . 71 , 73 , 75 , 77 , 79 , 81 , 83 , 85 reformatted tables. 98 added ? sts-1/au-3/au-4 pointer generation ? section. changed ? tu/vt pointer generation ? section. 100 changed ? general ? section. 105 changed paragraphs below figure 38 . 108 changed first four paragraphs of ? low order virtual concatenation with lcas ? section. 109 changed first four paragraphs of ? high order virtual concatenation without lcas ? section. 110 changed paragraph above figure 45 . 111 changed paragraph above figure 46 . 112 changed first four paragraphs of ? high order virtual concatenation with lcas ? section. 113 added ? configuration ? section. 115 added ? differential delay compensation ? section. 118 changed the diagram of figure 48 . 119 changed ? ethernet mac blocks ? section. 120 added ? ethernet half duplex ? section. 122 changed ? flow control operation ? section. 124 changed ? encapsulation / decapsulation ? section. 133 changed ? gfp host extraction of management/control frames ? title and text above tables. 172 changed ? sdram controllers ? section. 175 added ? reset operation ? section. 194 added ? performance counters ? section. 199 updated ? package information ? section. 200 updated ? ordering information ? section. 202 updated ? standards documentation sources ? section. 204 changed ? list of data sheet changes ? section. page number of updated data sheet summary of the change - 206 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 -notes- transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. product preview information docu- ments contain information on products in their formative or design phase of develop- ment. features, characteristic data and other specifications are subject to change. contact transwitch applications engineer- ing for current information on this product. - 207 of 208 - product preview txc-04212-mb, ed. 2 ethermap-12 txc-04212 data sheet proprietary transwitch corporation information for use solely by its customers product preview thi s product p re view data s he et contains preliminary information w h ich may be s ubject to change november 2003 -notes- transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 |
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